Via Offset for BEOL Delamination in Microelectronics Packaging
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Solution Overview
Problem
Prior microelectronic assemblies experience delamination in the back-end-of-line (BEOL) due to tensile stress on vias in peripheral regions of the chip, exacerbated by the use of low k dielectric materials, which is not effectively addressed by existing co-centered via, under bump metallization (UBM), and solder bump configurations.
Innovation Solution
The solution involves shifting the via towards the center of the chip or shifting the UBM towards the peripheral regions, thereby altering the stress distribution from tensile to compressive, reducing delamination by misaligning the via and UBM within the same horizontal row, allowing for reduced tensile stress on the via that connects the first-level interconnects to the BEOL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the via, UBM, and bump are co-centered in prior art microelectronic assemblies, then the manufacturing process is simple and straightforward, but tensile stress concentrates on the via in peripheral regions causing delamination in the BEOL
Solution Approach 1:
The patent applies asymmetry by offsetting the via from the center of the UBM and bump structure. Specifically, the via is positioned closer to the center of the chip rather than being co-centered with the UBM and bump. This asymmetric positioning changes the stress distribution pattern, moving the via away from the high tensile stress region that occurs at the edge of the UBM during chip attachment, thereby reducing delamination risk in the BEOL while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies local quality by creating a non-uniform stress distribution through via offsetting. The via is strategically positioned to experience compressive or reduced tensile stress locally, while other regions of the UBM-bump structure accommodate the stress differently. This localized stress management protects the via-UBM interface from delamination without requiring changes to the overall co-centered manufacturing approach
2Reliability
If low k dielectric materials are used to meet performance requirements, then the device performance is improved, but the BEOL becomes more prone to delamination under tensile stress
Solution Approach 1:
The patent applies preliminary anti-action by proactively offsetting the via from the high stress region before the delamination problem can occur. The via is pre-positioned in a location that anticipates and counteracts the tensile stress forces that will arise during chip attachment and operation. This preventive measure specifically protects low k dielectric BEOL structures from delamination without compromising device performance
Solution Approach 2:
The patent applies parameter changes by modifying the spatial parameter (via position) relative to the UBM and bump structure. By changing the via's radial position from co-centered to offset, the stress distribution parameters in the BEOL are fundamentally altered, reducing tensile stress concentration on the via-UBM interface and thereby protecting low k dielectric materials from delamination
Data Source
AI summary
The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip.