Via Opening Etching for Contact Pad Integrity in Semiconductor Wafers

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Solution Overview

Problem

Conventional patterning techniques for forming via openings in semiconductor wafers damage contact pads, affecting the reliability of semiconductor devices during the wafer singulation process.

Innovation Solution

A two-step etching process is employed to form via openings in the insulating layer on semiconductor wafers, where a first etching step partially removes the insulating layer without damaging the contact pads, followed by a second etching step to completely expose the pads without harming them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional patterning techniques are used to form via openings in the insulating layer, then the via openings are formed, but the contact pads are damaged

Engineering Contradiction:
Improvevia opening formationVSAvoidcontact pad integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The etching process is divided into multiple sequential steps (first etching step, second etching step, and optionally third etching step), where each step removes a portion of the insulating layer progressively. This segmentation allows control over the etching depth to expose contact pads while preventing damage through gradual material removal rather than single-step aggressive etching.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first etching step partially removes the insulating layer to a controlled depth that exposes the contact pads without completely removing the insulating layer. This partial action achieves the necessary exposure while maintaining protective coverage, and subsequent steps complete the exposure only where needed without excessive removal that would damage the pads.

Inventive Principle:
Principle #16Partial or excessive action

2Productivity

If a single-step etching process is used to expose contact pads, then the pads are exposed quickly, but the pads are damaged during the process

Engineering Contradiction:
Improvepad exposure speedVSAvoidcontact pad integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The single-step etching process is segmented into multiple sequential etching steps, each removing a portion of the insulating layer. This maintains productivity by systematically progressing through the layers while improving reliability by controlling the exposure process to prevent pad damage through gradual rather than abrupt material removal.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first etching step performs preliminary removal of the insulating layer to a controlled depth before the second etching step completes the exposure. This preliminary action prepares the structure for final pad exposure while preventing damage by stopping before complete removal, allowing subsequent steps to finish the process safely.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively exposes contact pads without damaging them, enhancing the reliability and integrity of the semiconductor devices by maintaining the structural integrity of the pads throughout the process.

Implementation Method 1

performing a first etching step for partially removing a portion of the insulating layer corresponding to the contact pad; and performing a second etching step for removing the remaining insulating layer in the at least one via opening

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS11990431B2Semiconductor structures with via openings and methods of making the same
Publication Date: 2024.05.21 PEP INNOVATION PTE LTD
  • US11990431B2 patent drawing
  • US11990431B2 patent drawing
  • US11990431B2 patent drawing

AI summary

The present disclosure discloses a semiconductor structure having an insulating layer disposed on a wafer active surface of a semiconductor wafer for covering the wafer active surface. The insulating layer may be a protective layer in some embodiments and a cover layer in other embodiments. The insulating layer has via openings to expose contact pads for leading out electrical connections. In particular, the via openings are formed by a multi-step etching process (such as a two-step etching process) without damaging the contact pads. The two-step etching process includes a first laser etching process using normal pulse (P) and normal energy to form partial via openings in the cover layer. The second etching process includes either a laser etching process using low P and low E or a plasma etching process. The second etching process avoids damaging the contact pads.