Via-Pad and Via-Plane Structures With Single-Exposure Alignment
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Solution Overview
Problem
Conventional package substrate manufacturing techniques require multiple lithography exposure process steps, leading to alignment errors and larger feature sizes, which hinder the formation of accurately aligned and smaller via-pad and via-plane structures in integrated circuit (IC) packages.
Innovation Solution
The use of a single lithography exposure process with a grayscale mask to pattern conductive via-pad and via-plane structures, allowing for improved alignment and smaller feature sizes by differently exposing areas of the photoresist to varying levels of electromagnetic energy, enabling the formation of conductive vias and bridges within dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography exposure process steps are used, then alignment errors increase and feature sizes become larger, but manufacturing process robustness is improved
Solution Approach 1:
The patent combines multiple lithography exposure steps into a single exposure process by using a grayscale mask that contains multiple patterns (via patterns, pad patterns, and alignment mark patterns) that are simultaneously exposed and developed. This merging of multiple exposure steps into one eliminates the cumulative alignment errors that occur when multiple separate exposures are performed, while also reducing the overall process complexity and number of process steps.
Solution Approach 2:
The patent introduces a grayscale mask as an intermediary element that enables single-exposure formation of multiple patterns. The grayscale mask acts as a mediator between the light source and the photoresist, allowing different regions of the photoresist to receive different amounts of light energy in a single exposure step, thereby creating multiple patterns with precise alignment without requiring multiple exposure steps.
2Ease of manufacture
If multiple lithography exposure process steps are used, then manufacturing complexity increases, but process robustness is improved
Solution Approach 1:
The patent merges multiple lithography exposure steps into a single exposure process by incorporating multiple patterns (via, pad, alignment marks) into one grayscale mask. This reduces the total number of process steps, simplifies the manufacturing流程, and eliminates the need for multiple mask alignments, thereby improving ease of manufacture while reducing process complexity.
Solution Approach 2:
The patent performs preliminary action by pre-designing the grayscale mask to contain all necessary patterns (via patterns, pad patterns, and alignment mark patterns) before the exposure process. This preliminary preparation of the mask allows all patterns to be formed in a single exposure step, eliminating the need for subsequent alignment and exposure operations, thereby simplifying the manufacturing process.
3Manufacturing precision
If conventional multi-step lithography is used, then alignment errors occur, but process robustness is maintained
Solution Approach 1:
The patent combines multiple exposure steps into one single exposure process using a grayscale mask, which eliminates the cumulative alignment errors that occur in multi-step processes. All patterns (via, pad, alignment marks) are exposed and developed simultaneously in one step, ensuring precise alignment and reliable feature size control without the variability introduced by multiple sequential exposures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, better-aligned via-pad and via-plane structures in IC packages, reducing manufacturing complexity and cost while achieving improved results, using standard tools and materials.
Implementation Method 1
differently exposing areas of the photoresist to varying levels of electromagnetic energy
Data Source
AI summary
Disclosed herein are via-trace-via structures with improved alignment, and related devices and methods. For example, in some embodiments, an integrated circuit (IC) package support may include a conductive structure having an aperture; a conductive via at least partially nested in the aperture in the conductive structure; and a conductive bridge spanning between and in contact with the conductive structure and the conductive via. In some embodiments, the conductive structure is a conductive pad. In some embodiments, the conductive structure is a conductive plane.