Through-Substrate Via Passivation Layout to Prevent Bending
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration and reliable electrical connections through conductive vias, particularly in stacked semiconductor structures.
Innovation Solution
A semiconductor device design featuring a substrate with a first passivation pattern having a recess region and a second passivation pattern that covers the via structure, along with a pad structure, ensuring a flat top surface and increased contact area, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a via structure penetrates through the substrate and passivation patterns, then electrical connection speed is improved, but the via structure may bend during polishing processes reducing reliability
Solution Approach 1:
The patent applies preliminary action by forming a recess region in the first passivation pattern before depositing the second passivation pattern. This pre-prepared structure allows the second passivation pattern to fill the recess and provide support to the via structure before polishing occurs, preventing bending during the polishing process while maintaining the via's electrical connection function.
Solution Approach 2:
The second passivation pattern acts as an intermediary element between the first passivation pattern and the via structure. It fills the recess region and provides mechanical support to the via structure, preventing it from bending during polishing while allowing electrical signals to pass through the via to the connection terminal.
2Reliability
If the pad structure bottom surface is at a higher level than the recess region bottom surface, then contact area is increased improving reliability, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes vertical dimensionality by creating a recess region that extends downward from the first passivation pattern surface. The pad structure is then formed at a higher level, contacting the second passivation pattern that fills the recess. This vertical arrangement increases the contact area and improves reliability without requiring additional lateral complexity in the manufacturing process.
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate including a first surface and a second surface that are opposite to each other, a via structure that penetrates the substrate, a first passivation pattern disposed on the first surface of the substrate and extending onto an upper sidewall of the via structure, and a second passivation pattern disposed on the first passivation pattern and exposing an uppermost surface of the first passivation pattern. At least a portion of the second passivation pattern is externally exposed. The first passivation pattern includes at least one selected from oxide and silicon oxide. The second passivation pattern includes at least one selected from nitride and silicon nitride.