Through-Substrate Via Passivation for Flat Contact Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration and reliability due to the development of reliable conductive vias for electrical connections between stacked semiconductor chips.
Innovation Solution
A semiconductor device design featuring a substrate with a first passivation pattern having a recess region and a second passivation pattern that exposes the via structure, along with a pad structure on the second passivation pattern, ensuring a flat top surface of the via structure through the use of multiple passivation layers and a polishing process to prevent bending during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via structure penetrates the substrate to enable electrical connections, then electrical connectivity between stacked chips is improved, but the via structure may bend or deform during manufacturing processes, reducing reliability
Solution Approach 1:
The passivation pattern is formed to cover and protect the via structure before subsequent manufacturing processes occur. This preliminary protective action prevents the via structure from bending or deforming during later processing steps, maintaining its straightness and electrical connection reliability.
Solution Approach 2:
The passivation pattern acts as an intermediary protective layer between the via structure and external mechanical stresses. This intermediate layer absorbs or distributes forces that would otherwise directly affect the via structure, preventing deformation while allowing the via to maintain its electrical connectivity function.
2Ease of operation
If the via structure is exposed on the surface, then electrical connections are accessible, but the via structure is vulnerable to damage and contamination, reducing device reliability
Solution Approach 1:
The passivation pattern is selectively positioned to cover specific regions around the via structure while leaving the via top surface exposed. This local differentiation allows the via to remain accessible for electrical connections while the surrounding areas are protected, achieving both accessibility and protection simultaneously.
Solution Approach 2:
The protective passivation structure is segmented into different regions: areas that cover and protect the via sidewalls and surrounding substrate, and areas that leave the via top surface exposed for electrical contact. This segmentation enables simultaneous achievement of protection and accessibility.
3Reliability
If multiple passivation patterns are used to protect the via structure, then reliability is improved, but the device structure becomes more complex
Solution Approach 1:
Multiple passivation layers and patterns are merged into an integrated protective structure that simultaneously provides mechanical support, contamination protection, and structural stability. By combining these functions into a unified passivation system, the design achieves high reliability without proportionally increasing complexity.
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate including a first surface and a second surface that are opposite to each other, a via structure that penetrates the substrate, a first passivation pattern disposed on the first surface of the substrate and extending onto an upper sidewall of the via structure, and a second passivation pattern disposed on the first passivation pattern and exposing an uppermost surface of the first passivation pattern. At least a portion of the second passivation pattern is externally exposed. The first passivation pattern includes at least one selected from oxide and silicon oxide. The second passivation pattern includes at least one selected from nitride and silicon nitride.