Interconnect Via Patterning With Dielectric Pillars for CMP Flatness
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Solution Overview
Problem
In integrated circuit fabrication, the use of ultra-low-k dielectric materials in the back end of line (BEOL) process can lead to surface defects due to low density of features, causing non-flat surfaces during chemical-mechanical planarization, which is exacerbated by the lack of effective chemical-mechanical planarization stops.
Innovation Solution
The formation of interconnect structures that include metal lines, vias, and dielectric pillars with an ultra-low-k dielectric material, where the height of the dielectric pillars and vias is equal to the metal lines, and the use of dummy vias to increase feature density and act as a chemical-mechanical planarization stop, ensuring a flatter surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ultra-low-k dielectric material is used in BEOL process, then signal integrity is improved, but surface flatness deteriorates due to low feature density
Solution Approach 1:
Dielectric pillars are formed in advance during the same fabrication process as metal lines and vias, ensuring they are ready to serve as CMP stops before the CMP process begins. This preliminary formation ensures uniform feature density across the wafer surface prior to planarization
Solution Approach 2:
Dielectric pillars are strategically positioned in regions where feature density is insufficient, creating local variations in feature distribution. This ensures that areas with low natural feature density have additional CMP stop structures, achieving uniform CMP performance across different regions of the wafer
2Device complexity
If feature density is low in ultra-low-k dielectric regions, then manufacturing complexity is reduced, but CMP process control worsens
Solution Approach 1:
The physical and chemical parameters of the dielectric material are optimized to achieve ultra-low-k properties while maintaining compatibility with CMP processing. The dielectric pillars use the same ultra-low-k material with controlled density and composition to ensure they function effectively as CMP stops
Solution Approach 2:
Dielectric pillars serve as intermediary structures that mediate between the ultra-low-k dielectric material and the CMP process. These pillars act as physical markers and mechanical stops that enable the CMP process to maintain control even in regions with otherwise low feature density
Data Source
AI summary
An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.