Self-Aligned Via Patterning Using Block Copolymer Self-Assembly
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in patterning extremely small vias with small pitches, where overlay control and critical dimension uniformity are difficult to achieve with current lithographic processes, especially as feature sizes approach 70 nanometers or less, due to limitations in lithographic equipment resolution and the need for multiple masks, which increases costs and complexity.
Innovation Solution
The implementation of a self-aligned via and plug patterning method using directed self-assembly (DSA) and selective growth mechanisms, where an underlying metal layer serves as a template to direct the formation of vias and plugs, reducing reliance on conventional top-down lithography for alignment and improving electrical contact by reversing the interconnect fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern small vias, then overlay control and critical dimension uniformity are maintained at larger feature sizes, but manufacturing precision deteriorates as feature sizes approach 70 nanometers or less
Solution Approach 1:
The patent inverts the conventional top-down lithographic approach by using a bottom-up self-assembly mechanism. Instead of using lithography to define via locations from above, the method allows vias to self-assemble from the previous metal layer upward through directed self-assembly of block copolymers, which naturally form patterns at the desired pitch without requiring high-resolution lithographic printing
Solution Approach 2:
The patent employs self-service by utilizing the intrinsic properties of block copolymer materials to automatically form ordered patterns at nanoscale dimensions. The system uses the natural micellization and self-assembly behavior of block copolymers to define via locations, eliminating the need for external lithographic patterning tools to achieve the required precision at sub-70nm pitch
2Manufacturing precision
If multiple lithographic masks are used to achieve small via pitches, then via pitch resolution is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent replaces the mechanical/optical lithographic scanning system with a chemical self-assembly system. Instead of using complex multi-mask lithographic processes that require precise alignment and multiple scanning passes, the method uses block copolymer self-assembly that naturally forms the required patterns through chemical and physical self-organization, eliminating the need for multiple lithographic masks
Solution Approach 2:
The patent changes the fundamental parameter from lithographic resolution (optical/electromagnetic) to block copolymer domain size (chemical/physical). By controlling the block copolymer composition, molecular weight, and self-assembly conditions, the via pitch is determined by material parameters rather than lithographic tool parameters, enabling sub-70nm pitch without multiple masks
3Length of moving object
If shrink technologies are used to reduce via critical dimensions, then via size is reduced, but line width roughness and critical dimension uniformity deteriorate
Solution Approach 1:
Instead of shrinking the lithographic pattern to reduce via size (which amplifies roughness and uniformity issues), the patent inverts the approach by allowing the block copolymer self-assembly process to naturally form the via pattern at the target size. The via critical dimension is defined by the block copolymer domain size rather than by lithographic shrinkage, resulting in smoother walls and better uniformity
Solution Approach 2:
The patent introduces block copolymers as an intermediary material that mediates between the previous metal layer and the final via structure. The block copolymers self-assemble into ordered domains that serve as templates for via formation, providing a natural length scale that defines the via critical dimension without requiring aggressive lithographic shrinking that would compromise uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more robust interconnect fabrication with improved overlay control and reduced process complexity, allowing for smaller feature sizes and pitches without compromising critical dimension uniformity, thereby overcoming the limitations of traditional lithographic methods.
Implementation Method 1
forming a self-assembled micellar structure of a block copolymer
Data Source
AI summary
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.