Self-Aligned Via Pedestal for IC Interconnect Misalignment
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Solution Overview
Problem
As IC feature size and spacing shrink, aligning vias with underlying metal wires becomes increasingly challenging, leading to misalignment errors that can cause electrical shorts or time-dependent dielectric breakdown, resulting in premature device failure or performance degradation.
Innovation Solution
A self-aligned interconnect via structure is developed, featuring a conductive pedestal that caps the overlay region between misaligned metal conductors, preventing the via from contacting adjacent metal wires, and a conductive liner is formed on the pedestal and sidewalls, ensuring the via is filled with conductive material without entering the substrate between metal conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard interconnect via methodology is used, then fabrication process is simple, but misalignment between vias and metal wires causes electrical shorts or dielectric breakdown
Solution Approach 1:
A conductive pedestal is formed in advance at the via location before the via etch and fill process. This pedestal extends laterally beyond the intended via footprint to cap the overlay region, preventing misaligned vias from contacting adjacent metal wires. The preliminary formation of this protective conductive structure eliminates electrical shorting risks without requiring changes to the core via fabrication methodology.
2Productivity
If feature size and spacing are shrunk, then IC density is increased, but alignment precision between vias and metal wires becomes more difficult to maintain
Solution Approach 1:
The conductive pedestal is designed to extend laterally beyond the via opening boundaries, creating a protective cap that actively prevents misaligned vias from contacting adjacent metal wires. This preliminary protective structure counteracts the harmful effects of overlay errors, enabling reliable operation even when alignment precision deteriorates due to scaled feature dimensions.
3Reliability
If conductive pedestal is added to prevent shorts, then reliability is improved, but fabrication process complexity increases
Solution Approach 1:
The conductive pedestal is formed using existing metallization layers and patterning processes already present in the backend-of-line fabrication sequence. The pedestal material is deposited and patterned to define the via location, then subsequently used as a self-aligned template for via formation. This self-service approach integrates the protective function into the existing manufacturing flow without requiring additional process steps or equipment.
Data Source
AI summary
A method of increasing a tolerance to misalignment errors in forming an interconnect via includes: providing a dielectric substrate including at least first and second adjacent metal conductors laterally from one another in a lower metal wiring layer of the integrated circuit; forming a capping layer over at least a portion of an upper surface of the substrate; forming an insulting layer on at least a portion of the capping layer; forming an opening through the insulating and capping layers to expose the first metal conductor; forming a conductive pedestal on the first metal conductor, the conductive pedestal capping an overlay region in the substrate between the first and second metal conductors resulting from misalignment of the opening relative to the first metal conductor; forming a conductive liner on sidewalls of the opening and on the conductive pedestal; and filling the opening with a conductive material to form the via.