Via Pillar Placement for Integrated Circuit Signal Delay
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Solution Overview
Problem
As integrated circuit features decrease in size, increased resistance in via paths leads to signal delay and power consumption issues, necessitating improvements in circuit design and layout to achieve lower power consumption and faster performance.
Innovation Solution
The strategic placement of via pillars at specific locations within the circuit, such as prior to fanout and between output and input pins, to reduce resistance and improve timing, while minimizing the complexity and resource usage of the circuit layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If critical dimensions of integrated circuits are decreased to enable smaller sizes, then device size is reduced, but resistance of circuit paths increases leading to higher power consumption and slower performance
Solution Approach 1:
The via structure is segmented into multiple parallel via pillars instead of a single via, distributing the current flow across multiple paths and reducing overall resistance without increasing the footprint area
Solution Approach 2:
Multiple via pillars are merged in parallel between the same two conductive layers to create a combined conductive path that maintains low resistance while occupying minimal space
2Loss of time
If via pillars are added to reduce resistance and improve timing, then signal propagation delay is reduced, but circuit layout complexity and resource usage increase
Solution Approach 1:
Via pillars are selectively placed only at specific locations where timing optimization is needed (e.g., high-fanout paths, critical signal paths) rather than uniformly across the entire circuit, reducing unnecessary complexity
Solution Approach 2:
The via pillar placement is determined during the place-and-route design phase based on timing analysis, allowing proactive optimization of critical paths before final circuit fabrication
Data Source
AI summary
In examples described herein, methods for via pillar placement and an integrated circuit design including a via pillar are described. In some instances, a path within an integrated circuit or proposed integrated circuit design can be identified as having negative slack. In such instances, in particular where the path includes a fanout to input pins of receivers, a via pillar can be inserted at a location prior to fanout of the path. The via pillar can be inserted, for example, proximate to the fanout, but between the fanout and an output pin of a driver that is connected to the path.