Via Pillar ECO for IC Timing Constraint Satisfaction
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Solution Overview
Problem
Advanced semiconductor technologies face challenges in designing and fabricating ICs due to increasing complexity and density, leading to design errors such as timing violations, which require costly redesigns, and existing layout refinement procedures are inefficient in managing timing issues without unnecessary power or area consumption.
Innovation Solution
The introduction of via pillar (VP) structures during the engineering change order (ECO) phase in the placement and routing operation reduces resistance and effectively addresses timing errors by allowing efficient data association between the placement-and-routing phase and the ECO phase, enabling better trade-offs between power, area, and design requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via pillar (VP) structures are introduced during ECO phase, then timing errors are effectively addressed and resistance is reduced, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent applies preliminary action by identifying and marking via pillar candidate locations during the placement and routing phase, before the ECO phase begins. This pre-positioning of via pillar structures allows for efficient timing correction during ECO without adding significant complexity, as the structural modifications are predetermined rather than improvised during the correction phase.
Solution Approach 2:
The patent introduces via pillar structures as intermediary elements between existing circuit components. These via pillars serve as mediating structures that provide additional conduction paths and reduce resistance between logic cells, effectively addressing timing errors while maintaining a systematic approach to layout modification that manages complexity.
2Reliability
If via pillar (VP) structures are introduced during ECO phase, then timing errors are effectively addressed, but ease of manufacture deteriorates due to additional layout refinement procedures
Solution Approach 1:
By pre-identifying via pillar candidate locations during placement and routing and marking them for potential ECO operations, the patent simplifies the ECO phase manufacturing process. The via pillar structures are not created from scratch during ECO but rather activated or modified from pre-planned locations, reducing the complexity of layout refinement procedures.
Solution Approach 2:
The patent modifies manufacturing ease by changing the parameter of via pillar presence or activation state rather than fundamentally altering the manufacturing process. During ECO, the system selectively activates or modifies via pillar structures at predetermined locations, which is a simpler parameter change compared to introducing entirely new manufacturing procedures for timing correction.
3Ease of manufacture
If conventional layout refinement procedures are used, then manufacturing simplicity is maintained, but timing errors cannot be effectively corrected without unnecessary power or area consumption
Solution Approach 1:
The patent segments the layout refinement process into two distinct phases: placement and routing phase where via pillar candidates are identified and marked, and ECO phase where timing errors are corrected using these pre-identified structures. This segmentation allows conventional simple procedures to be combined with targeted via pillar modifications, achieving timing correction without unnecessary power or area consumption.
Solution Approach 2:
The via pillar structures serve as intermediary elements that bridge conventional layout refinement procedures and timing error correction. By introducing these intermediate structures at specific candidate locations, the patent enables effective timing correction while maintaining the simplicity of conventional procedures for non-critical areas, avoiding unnecessary power or area consumption.
Data Source
AI summary
A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout comprises a first cell coupled to a metallization unit and the metallization unit includes one of a first via pillar (VP) structure and a single-via stacking structure; determining whether the layout meets a timing constraint; and performing, in response to the layout being determined as failing the timing constraint, an engineering change order (ECO) operation by replacing the metallization unit with a second VP structure.