Via Partitioning Using Plating Resist for Signal Integrity
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Solution Overview
Problem
The existing methods for reducing stubs in plated via structures of printed circuit boards (PCBs) are inefficient and costly, as they require sequential processing, are prone to errors, and can damage the PCBs, leading to signal degradation and increased production costs.
Innovation Solution
The use of plating resist to electrically isolate portions of the via structure, allowing only necessary conductive material to be formed, thereby reducing or eliminating stubs and improving signal integrity by partitioning the via structure into isolated segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plating resist is used to partition via structures, then manufacturing precision and signal integrity are improved, but device complexity increases due to additional processing steps
Solution Approach 1:
The plating resist is applied to the via structures before the plating process begins, pre-positioning the material that will define the partition boundaries. This preliminary action ensures that the resist is in place to control conductive material deposition from the start, achieving precise partitioning without requiring complex post-processing steps.
Solution Approach 2:
The plating resist acts as an intermediary material between the via structure and the conductive plating material. It mediates the plating process by selectively allowing or preventing conductive material deposition in specific regions, thereby achieving precise via partitioning while simplifying the overall process compared to multiple sequential plating operations.
2Manufacturing precision
If sequential processing is used to manufacture vias with short stubs, then manufacturing precision is improved, but productivity decreases due to increased production time
Solution Approach 1:
The invention merges the via partitioning function with the standard plating process by applying plating resist to defined via locations. This combination allows multiple via structures to be processed simultaneously in a single plating operation, achieving precise stub length control while maintaining high productivity through parallel processing of multiple vias rather than sequential operations.
3Reliability
If backdrilling is used to remove stubs, then signal integrity is improved by reducing parasitic elements, but manufacturing precision deteriorates due to drilling inaccuracies
Solution Approach 1:
The plating resist is applied in advance to define the exact boundaries where conductive material should be deposited. This preliminary positioning prevents excessive conductive material formation at the via ends from the start, eliminating the need for backdrilling and associated inaccuracies while maintaining signal integrity through precise initial partitioning.
Solution Approach 2:
Instead of trying to remove harmful stubs through backdrilling (which introduces new problems), the invention converts the approach by using plating resist to prevent harmful conductive material deposition in the first place. The resist material itself becomes the beneficial element that defines precise via boundaries, turning a subtraction process (backdrilling) into a controlled addition process (selective plating).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for faster and more efficient production of PCBs with improved signal integrity and reduced costs by minimizing signal degradation and avoiding the inaccuracies associated with backdrilling, while enabling higher wiring density and reliability.
Implementation Method 1
The plated via structure is effectively partitioned into a plurality of electrically isolated portions by selectively depositing plating resist in a sub-composite structure for making the PCB stackup
Data Source
AI summary
A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.


