Via and Plug Architectures for IC Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit (IC) manufacturing lies in achieving precise formation of vias and plugs at nanometer scales, as current lithographic processes struggle with resolution limitations, leading to increased costs due to the need for multiple masks and complex patterning techniques, especially at pitches below 70 nanometers.
Innovation Solution
The use of one-dimensional grating mask structures and multi-colored interlayer dielectric layers allows for the fabrication of dual-damascene interconnects with dielectric plugs and vias, employing pitch splitting techniques to define metal line ends and vias using a single lithographic plate, thereby reducing the complexity and cost of mask sets required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to form vias at small pitches, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to resolution limitations at pitches below 70 nanometers
Solution Approach 1:
The patent applies segmentation by dividing the via formation process into distinct stages: forming openings in the first ILD layer, depositing conductive material, forming openings in the second ILD layer, and backfilling. This segmented approach allows each stage to be optimized independently, achieving precise via formation at small pitches while managing overall process complexity through systematic breakdown of the manufacturing steps.
2Manufacturing precision
If multiple lithographic masks are used to achieve small pitch patterning, then manufacturing precision improves, but device complexity increases due to the need for multiple masks and complex patterning techniques
Solution Approach 1:
The patent employs preliminary action by forming the first ILD layer with embedded conductive material and via openings before forming the second ILD layer. This preliminary structuring allows subsequent patterning steps to work with pre-defined features, reducing the need for multiple lithographic masks and complex patterning techniques while maintaining precision at small pitches.
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional structuring by forming trenches through multiple ILD layers and filling them with conductive material. This dimensional approach allows precise via and line end formation by controlling etch depths and layer interfaces rather than relying solely on lithographic resolution, thereby reducing mask complexity.
3Productivity
If via sizes are scaled down to maintain circuit density, then productivity improves, but manufacturing precision becomes more difficult to achieve due to faster scaling of critical dimensions compared to lithographic resolution
Solution Approach 1:
The patent replaces reliance on mechanical lithographic resolution with chemical and physical processes: anisotropic etching to create vertical sidewalls, selective deposition to fill trenches, and controlled removal of sacrificial materials. These processes enable precise critical dimension control at scaled via sizes by using self-aligned mechanisms and material property differences rather than purely optical resolution.
Solution Approach 2:
The patent changes material parameters by using different dielectric materials with distinct etch selectivities for the first and second ILD layers, and by controlling the physical and chemical properties of conductive fill materials. These parameter changes enable precise via formation at small dimensions through selective processing rather than relying solely on lithographic critical dimension control.
Data Source
AI summary
Methods and architectures for forming metal line plugs that define separations between two metal line ends, and for forming vias that interconnect the metal lines to an underlying contact. The line plugs are present in-plane with the metal lines while vias connecting the lines are in an underlying plane. One lithographic plate or reticle that prints lines at a given pitch (P) may be employed multiple times, for example each time with a pitch halving (P/2), or pitch quartering (P/4) patterning technique, to define both metal line ends and metal line vias. A one-dimensional (1D) grating mask may be employed in conjunction with cross-grating (orthogonal) masking structures that are likewise amenable to pitch splitting techniques.