Via Plug Loading Effect Reduction in Semiconductor Etching
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Solution Overview
Problem
Conventional techniques for semiconductor manufacturing, particularly in dual-damascene etching, face challenges in reducing the loading effect caused by pattern diversity due to the use of deep ultraviolet light absorbing oxide (DUO) materials, which often result in inadequate thickness uniformity and increased complexity.
Innovation Solution
The method involves forming a via plug during the etching process to reduce loading effects, using a sacrificial layer with specific dimensions and a spin coating process to achieve uniformity in DUO layer thickness, and employing a combination of etching and deposition steps to maintain consistent etching depths across the semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If deep ultraviolet light absorbing oxide (DUO) materials are used to fill via openings, then the loading effect is reduced, but the thickness uniformity deteriorates and process complexity increases
Solution Approach 1:
The patent divides the via opening filling process into two distinct stages: first forming a via plug with sacrificial material, then forming the DUO layer over the entire surface. This segmentation allows the DUO layer to be deposited uniformly across the substrate without being affected by the underlying via structures, thereby maintaining thickness uniformity while still providing loading effect reduction benefits.
Solution Approach 2:
The via plug is formed in advance before depositing the DUO layer. This preliminary action creates a stable foundation that prevents the DUO material from sinking into via openings during deposition, ensuring uniform thickness. The via plug serves as a placeholder that maintains the via opening structure intact during the DUO formation process.
2Object-affected harmful factors
If deep ultraviolet light absorbing oxide (DUO) materials are used to fill via openings, then the loading effect is reduced, but the process complexity increases
Solution Approach 1:
The complex task of forming uniform DUO layers over via openings is segmented into manageable steps: forming via plugs, depositing DUO material, and selective removal. This segmentation simplifies each individual step while achieving the overall goal of reducing loading effects with uniform thickness control.
Solution Approach 2:
The via plug acts as an intermediary element between the substrate and the DUO layer. It temporarily occupies the via opening space during DUO deposition, preventing direct interaction between the DUO material and the via opening that would cause thickness non-uniformity. After serving its purpose, the via plug is selectively removed, leaving a clean interface for subsequent processing.
3Manufacturing precision
If via plugs are formed with specific dimensions, then the uniformity of DUO layer thickness is improved, but the manufacturing steps increase
Solution Approach 1:
The via plug is formed with specific local dimensions (height and width) that are optimized for its particular function of supporting the DUO layer. These localized dimensional specifications ensure that the DUO layer achieves uniform thickness over the via openings without requiring complex global process adjustments. The local quality of the via plug directly determines the uniformity of the overlying DUO layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the difference in DUO layer thickness, leading to improved uniformity and consistency in semiconductor fabrication, thereby minimizing the loading effect and enhancing the overall manufacturing process efficiency.
Implementation Method 1
a spin coating process to achieve uniformity in DUO layer thickness
Implementation Method 2
chemical dry etching process used for the manufacture of integrated circuits
Data Source
AI summary
Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.