Through-Substrate Via Insulation via Preliminary Polymer Filling
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Solution Overview
Problem
Conventional methods for manufacturing through-silicon vias face challenges in miniaturization and integration due to high aspect ratio ring-like grooves, leading to difficulties in filling insulating polymers and increasing parasitic capacitance and stress mismatch between silicon substrates and copper films.
Innovation Solution
A manufacturing method involving the formation of via holes in semiconductor substrates, filling with insulating via coating materials, and retaining a portion as a via coating film to reduce parasitic capacitance and stress mismatch, using a self-aligned process with a low dielectric constant insulating polymer and etching-resistant films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ring-like groove with high aspect ratio is formed in the silicon substrate to be filled with insulating polymer, then the parasitic capacitance is reduced and stress mismatch is minimized, but the filling process becomes difficult and miniaturization is hindered
Solution Approach 1:
The insulating polymer is applied in advance to fill the via hole before the etching process that forms the ring-like groove. This preliminary filling action ensures that the polymer is already in position to reduce parasitic capacitance and minimize stress mismatch, while avoiding the difficulty of filling high aspect ratio grooves formed after etching.
Solution Approach 2:
The conventional sequence of operations is inverted: instead of forming the ring-like groove first and then filling it with insulating polymer, the insulating polymer is applied first to fill the via hole, and then the ring-like groove is formed by etching. This inversion resolves the filling difficulty while maintaining the electrical and mechanical benefits.
2Volume of moving object
If the silicon substrate is thinned to achieve miniaturization, then device size is reduced, but the difficulty of filling insulating polymer in high aspect ratio grooves increases
Solution Approach 1:
The insulating polymer is applied preliminarily before substrate thinning and groove formation. This ensures that the polymer filling occurs when the via hole has a more favorable geometry, avoiding the exacerbated aspect ratio problems that would result from thinning the substrate first.
Solution Approach 2:
The operation sequence is inverted so that insulating polymer filling occurs before substrate thinning and groove formation, rather than after. This inversion allows miniaturization to proceed while maintaining ease of polymer filling.
3Ease of manufacture
If conventional manufacturing methods are used with high aspect ratio grooves, then through-vias can be formed, but parasitic capacitance increases and stress mismatch occurs
Solution Approach 1:
The insulating polymer is applied in advance to fill the via hole before the etching process creates the ring-like groove. This ensures the polymer is already in position to provide electrical isolation (reducing parasitic capacitance) and mechanical buffering (minimizing stress mismatch), while the subsequent etching process still successfully forms the through-via structure.
Solution Approach 2:
The conventional sequence is inverted: insulating polymer filling is performed before groove formation through etching, rather than after. This inversion ensures that the polymer is present to provide electrical and mechanical benefits while avoiding the difficulties of filling high aspect ratio grooves.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables miniaturization and higher integration of semiconductor devices with reduced parasitic capacitance and stress mismatch, achieving reliable and cost-effective three-dimensional integration of semiconductor circuits.
Implementation Method 1
This reduces parasitic capacitance caused by the through-via
Implementation Method 2
stress mismatch caused by a difference in the coefficient of thermal expansion between the silicon substrate 101 and the through-via (copper film 111) can be reduced
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including a first surface serving as an element formation surface, and a second surface opposite to the first surface; a through-via penetrating the semiconductor substrate; an insulating via coating film formed between a sidewall of the through-via and the semiconductor substrate; and an insulating protective film formed on the second surface of the semiconductor substrate. The via coating film and the protective film are different insulating films from each other.


