Via Formation Using Post-Silicide Spacer Protection
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is aligning via holes to source/drain regions between closely spaced gate electrodes, which often results in misalignment and excessive etching into sidewall spacers, leading to reliability issues and altered transistor performance as critical dimensions scale.
Innovation Solution
The method involves forming a first sidewall spacer, followed by a silicidation process and an additional sidewall spacer of a different material, protecting the first spacer during via hole etching through an interlayer dielectric. This approach ensures precise via formation by using a post-silicide spacer and an etch stop layer with selective etch characteristics to prevent damage to the sidewall spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If adjacent gate electrodes are placed close together to optimize space usage, then area efficiency is improved, but alignment precision of via holes deteriorates
Solution Approach 1:
The patent applies preliminary action by forming an etch stop layer and a second sidewall spacer before via hole formation. The etch stop layer is deposited conformally over the first sidewall spacer and gate electrodes, and the second sidewall spacer is formed after silicidation. These preliminary structures are specifically designed to protect the first sidewall spacer during subsequent via etching processes, ensuring precise via alignment even when gate electrodes are closely spaced.
Solution Approach 2:
The patent introduces an etch stop layer as an intermediary between the first sidewall spacer and the via etching process. This etch stop layer selectively protects the first sidewall spacer during via hole formation, acting as a mediator that allows the via to be etched precisely to the source/drain region without damaging the critical first sidewall spacer structure. The second sidewall spacer serves as another intermediary protective element.
2Area of stationary object
If via holes are formed close to gate electrodes, then area efficiency is improved, but reliability deteriorates due to excessive etching into sidewall spacers
Solution Approach 1:
The patent forms the etch stop layer and second sidewall spacer in advance, before the via hole etching process. This preliminary action ensures that protective structures are already in place to prevent excessive etching into the first sidewall spacer, thereby maintaining device reliability while allowing via holes to be formed close to gate electrodes for area efficiency.
Solution Approach 2:
The etch stop layer serves as a cushioning protective layer that absorbs or prevents the harmful effect of excessive etching. By placing this layer beforehand, the patent cushions the first sidewall spacer from damage during via formation, ensuring that even if alignment is not perfect, the critical spacer structure remains intact and device reliability is maintained.
3Device complexity
If misalignment occurs during via formation, then manufacturing complexity is reduced, but reliability deteriorates due to excessive etching into sidewall spacers
Solution Approach 1:
The etch stop layer is deposited beforehand to provide a protective cushion against misalignment during via etching. This layer absorbs the impact of alignment variations, preventing the etch from reaching and damaging the first sidewall spacer. This approach maintains reliability without significantly increasing process complexity, as the etch stop layer formation is a standard deposition process.
Solution Approach 2:
The etch stop layer acts as an intermediary protective element between the via etching process and the first sidewall spacer. This mediator allows the etching process to proceed even with some misalignment, while the intermediary layer prevents the harmful effects from reaching the critical spacer structure, thereby maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively forms vias close to gate electrodes while protecting the sidewall spacers, improving alignment and reducing reliability issues, even with minimal misalignment, and maintains contact area without detrimental effects on semiconductor device performance.
Implementation Method 1
After source/drain region formation, a silicidation process results in a silicide region on the source/drain region
Data Source
AI summary
A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.