Via Formation Protecting Semiconductor Layers During Etching
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Solution Overview
Problem
In 3D integrated circuits, forming vias between semiconductor layers is challenging due to the risk of removing thin upper level layers during etching, which compromises contact quality and increases stray capacitance when attempting to thicken source and drain regions through local epitaxy.
Innovation Solution
A method involving the formation of a conductive protection material layer on the edge of the upper level semiconductor layer during etching, using electroless deposition, to protect the layer and ensure selective etching of insulating materials, thereby preventing removal of the upper layer and maintaining low stray capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If anisotropic etching is used to form a via between semiconductor layers, then the insulating layers are selectively etched to create the via opening, but the thin upper level semiconductor layer is partially or totally removed
Solution Approach 1:
A protection layer is formed on the upper level semiconductor layer before the etching process. This preliminary protective action prevents the thin upper layer from being removed during subsequent anisotropic etching of the insulating layers, thereby maintaining both via formation precision and upper layer integrity
Solution Approach 2:
A protection layer acts as an intermediary between the etching process and the upper level semiconductor layer. This intermediate layer is selectively etched away after via formation, having served its protective function during the critical etching step without compromising the upper layer
2Reliability
If the thickness of source and drain regions is increased through local epitaxy to improve contact quality, then contact surface area is increased, but stray capacitance between gate and source/drain regions increases
Solution Approach 1:
The protection layer is formed in advance before any epitaxial thickening. This allows the via to be formed with adequate contact area to the original thin layer, eliminating the need for subsequent local epitaxy to improve contact quality, thereby avoiding the harmful increase in stray capacitance
Solution Approach 2:
The protection layer is a temporary, disposable structure used only during the critical via formation step. It is selectively removed after serving its purpose, leaving no permanent modification to the upper layer that would increase capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables reliable via formation between semiconductor layers without compromising the upper layer's integrity, ensuring effective electrical contact and minimizing stray capacitance.
Implementation Method 1
fixating a layer of a protection material on said edge only
Implementation Method 2
c) deepening said opening by selectively etching the insulating material to reach the second lower level layer
Data Source
AI summary
A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.