Via Rail and Deep Via Structures Reduce Parasitic Capacitance
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Solution Overview
Problem
As semiconductor integrated circuits evolve with decreasing dimensions, reduced separations between conductive structures lead to increased parasitic capacitance, which affects device power consumption and performance.
Innovation Solution
The implementation of via rail and deep via structures, which are formed in different interconnect levels and dielectric layers, reduces parasitic capacitance by increasing separation between conductive structures and providing electrical connections without additional masks or gate density degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductive structures are placed closer together to increase functional density, then the number of interconnected devices per chip area increases, but parasitic capacitance increases leading to higher power consumption
Solution Approach 1:
The patent introduces via rail structures that extend vertically through multiple interconnect levels, transforming a two-dimensional routing problem into a three-dimensional solution. By placing via rails in vertical columns that span multiple metal layers, the design enables shorter horizontal wire segments while maintaining electrical connectivity, thereby reducing parasitic capacitance between adjacent conductors on the same plane while preserving functional density.
Solution Approach 2:
The via rail structure acts as an intermediary conductive element that provides alternative current paths. Instead of having long horizontal wires that closely approach each other (creating high parasitic capacitance), the via rail serves as a vertical mediator that connects to multiple interconnect levels, allowing signals to transfer between layers and reducing the need for closely-spaced horizontal routing.
2Loss of energy
If via rail structures are introduced to reduce parasitic capacitance, then power consumption decreases, but device complexity increases due to additional interconnect structures
Solution Approach 1:
The via rail structure serves multiple functions simultaneously: it provides vertical interconnect between different metal layers, acts as a shielding element to reduce parasitic capacitance between adjacent wires, and serves as a reference plane for signal routing. This multi-functionality reduces the need for separate structures dedicated to each function, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The interconnect system is segmented into distinct functional components: horizontal wire segments for signal routing, vertical via rail segments for inter-layer connectivity, and dielectric regions for isolation. This segmentation allows each component to be optimized independently for its specific function, managing complexity through modular design rather than requiring a monolithic complex structure.
3Loss of energy
If deeper vias are used to connect to lower interconnect levels, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The via rail structures are formed using the same patterning and etching processes as the standard via structures in the fabrication flow. By integrating via rail formation into existing process steps (such as using the same mandrel formation, deposition, and etch procedures), the patent achieves deep via connectivity without requiring separate high-precision alignment steps, thereby managing manufacturing precision requirements through process integration.
Data Source
AI summary
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.