Via Resistance Reduction in Phase Change Memory Devices
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Solution Overview
Problem
Conventional phase change memory devices face limitations in current flow due to high resistivity in the interlayer, which degrades programming operations, especially as device sizes reduce and contact pitch decreases, limiting maximum current flow and degrading memory cell performance.
Innovation Solution
Modifying the memory device manufacturing process to form vias after the interlayer and bit line are formed, allowing the via to directly contact the bit line and removing the high resistivity interlayer from the path between the decoder and memory cells, thereby enhancing current flow and thermal characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the interlayer is formed before the via to protect the bit line during manufacturing, then the bit line is protected from damage, but the via resistance increases due to the high resistivity of the interlayer material
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: first forming the interlayer and bit line, then selectively removing interlayer material to create via openings, and finally filling the vias with conductive material. This segmentation allows the interlayer to serve its protective function during bit line formation while eliminating its harmful resistive effect in the final via structure.
Solution Approach 2:
The patent extracts the high-resistivity interlayer material from the via region by forming via openings that remove the interlayer, exposing the bit line. This extraction eliminates the source of high via resistance while preserving the interlayer's protective benefits in regions where it remains intact.
2Area of stationary object
If the contact pitch is reduced to decrease device size, then the device footprint is reduced, but the via resistance increases and current flow is limited
Solution Approach 1:
The patent applies local quality by creating via openings with specific dimensions and positions that optimize the conductive path. The via structure provides a localized low-resistance connection point that compensates for the overall reduced contact pitch, maintaining current flow capability despite smaller device footprint.
Solution Approach 2:
The patent creates an asymmetric structure where the via opening removes interlayer material asymmetrically to expose the bit line, forming an optimized conductive path that differs from the symmetric interlayer deposition pattern, thereby reducing resistance in the constrained space.
3Reliability
If the via is formed before the interlayer to reduce via resistance, then the via has lower resistance, but the bit line is exposed to potential damage during subsequent manufacturing steps
Solution Approach 1:
The patent performs preliminary action by forming the interlayer and bit line structure first, establishing a protected and stable bit line before creating the via openings. This preliminary formation of the bit line under the protective interlayer reduces the risk of damage during subsequent via processing steps.
Solution Approach 2:
The patent inverts the conventional sequence by forming the interlayer before the via, opposite to the traditional approach of forming vias first. This inverted sequence allows the interlayer to protect the bit line during manufacturing while the subsequent via formation process selectively removes interlayer material to create low-resistance contact points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces via resistance, improves current flow, and maintains the beneficial properties of the interlayer between memory cells and bit lines, enhancing programming operations and reducing manufacturing costs and potential damage to conductive traces.
Implementation Method 1
high resistivity in the interlayer, which degrades programming operations... removes the high resistivity interlayer from the path between the decoder and memory cells, thereby enhancing current flow
Implementation Method 2
Joule heating may then induce a phase change transition, from the crystalline state to the amorphous state or from the amorphous state to the crystalline state
Implementation Method 3
the phase change memory stores information on the memory element by changing the phase of the memory element between amorphous and crystalline phases
Data Source
AI summary
One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the dielectric region and partially on a plurality of memory cells. The via has a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact.