Via Rework Process Using Underfill to Protect Via Profiles
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability due to issues such as enlargement and profile damage of via openings during the fabrication process.
Innovation Solution
The method involves forming an underfill or bottom filling layer to alleviate enlargement and profile damage of via openings by employing specific mask layers and reworking processes, including the use of underfill and top hard mask layers to pattern and etch the dielectric layers effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via opening formation processes are used during scaling down, then manufacturing complexity is reduced, but via opening enlargement and profile damage occur leading to decreased yield and reliability
Solution Approach 1:
The fabrication process is divided into multiple sequential steps: forming an initial hard mask layer, forming a first via opening, depositing an underfill layer, forming a second hard mask layer, and forming a final via opening. This segmentation allows each step to be optimized independently, preventing via opening enlargement and profile damage while maintaining manageable process complexity through systematic breakdown of the fabrication sequence.
Solution Approach 2:
The underfill layer is deposited before forming the final via opening pattern. This preliminary action protects the via opening profile from damage during subsequent etching processes and prevents enlargement by providing a stable base layer. The underfill layer is prepared in advance to ensure proper via opening formation without compromising profile precision.
2Reliability
If multiple mask layers and reworking processes are employed to prevent via opening damage, then yield and reliability improve, but manufacturing time and process steps increase
Solution Approach 1:
Multiple functions are combined into integrated process steps. The underfill layer serves both as a protective layer for via opening profile and as a base layer for subsequent hard mask deposition. The first and second hard mask layers are formed using similar photolithography processes, allowing standardization and reducing overall process time despite the increased number of steps.
Solution Approach 2:
The process utilizes controlled parameter changes at each stage: adjusting etch selectivity between different layers, controlling deposition thicknesses of mask and underfill layers, and optimizing photolithography exposure parameters. These parameter optimizations ensure that each additional step contributes maximally to reliability improvement while minimizing time consumption.
Data Source
AI summary
The present application discloses a method for fabricating a semiconductor device including providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening.