Interconnect Via Structure With Rounded Etch Stop for Fine Patterning
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Solution Overview
Problem
As semiconductor devices shrink, defining fine patterns in the exposure process becomes increasingly difficult, and there is a growing need for high integration and high-speed devices while maintaining reliability, which existing technologies struggle to address effectively.
Innovation Solution
A semiconductor device design that includes a substrate with a first dielectric layer, lower conductive lines, an etch stop layer with a rounded surface, a via-structure, and an upper conductive line, where the etch stop layer conformally covers the dielectric layer and lower conductive lines, and the rounded surface of the etch stop layer facilitates better via-fill margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor devices are shrunk to achieve smaller size and higher integration, then device density and functionality are improved, but the difficulty of defining fine patterns in the exposure process increases
Solution Approach 1:
The etch stop layer is configured with a rounded top surface instead of a flat surface. This curvature allows the via structure to be formed with better fill characteristics, as the rounded surface provides a gradual transition that facilitates material deposition and reduces void formation during via filling, thereby improving manufacturing precision for fine patterns
2Productivity
If device size is reduced to increase integration density, then more functions can be packed into smaller area, but exposure process margins are reduced making pattern definition increasingly difficult
Solution Approach 1:
The rounded top surface of the etch stop layer creates a geometric configuration that is more tolerant to variations in via filling processes. This curvature provides a built-in compensation mechanism that maintains via fill quality even when exposure process margins are reduced, enabling higher integration density without sacrificing manufacturing precision
3Manufacturing precision
If via-fill margin is improved by using a rounded etch stop layer surface, then via structure quality is enhanced, but additional process steps or complexity may be introduced
Solution Approach 1:
The etch stop layer is formed with a rounded top surface by controlling the deposition or formation parameters of the etch stop layer material. This parameter change (from flat to rounded surface) is achieved through process optimization rather than adding complex additional steps, thus improving via-fill margin while minimizing increases in device complexity
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.