Via Routing Structures for Semiconductor Layouts
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Solution Overview
Problem
As technology nodes scale down, traditional layout designs using diffusion contact flyovers increase the risk of unintentional transistor activation and drive up costs due to increased mask requirements for middle-of-line processes, particularly in 14 nm technology nodes and beyond.
Innovation Solution
Implementing via routing structures with self-aligned double patterning (SADP) processes that do not overlay gate or diffusion contacts, allowing for alternative routing without the need for complex handshake structures and reducing the number of masks required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If diffusion contact flyovers are used to implement cross-coupling-based designs, then routing flexibility is improved, but the risk of unintentional transistor activation increases and layout integrity deteriorates
Solution Approach 1:
The patent introduces an intermediary structure (the via routing structure with via hole) between the diffusion contact and the metal routing structure. This intermediary allows the metal routing to cross over the diffusion contact region without directly contacting it, thereby maintaining routing flexibility while preventing unintentional transistor activation and preserving layout integrity.
2Manufacturing precision
If traditional techniques are used to form diffusion contacts and metal1 layer structures, then tip-to-tip space requirements are met, but the number of masks increases and manufacturing costs increase
Solution Approach 1:
The patent merges the formation of the via routing structure with the existing diffusion contact and metal1 layer structure fabrication process. By integrating the via hole creation into the same manufacturing sequence, the patent achieves precise tip-to-tip spacing while avoiding the need for additional separate patterning steps that would increase mask count and manufacturing complexity.
3Area of moving object
If technology nodes scale down to meet decreasing size requirements, then device density is improved, but process integration risks increase
Solution Approach 1:
The patent resolves scaling-related process integration risks by transitioning from a planar routing approach to a three-dimensional via-based routing structure. This vertical dimension allows metal routing to pass over diffusion contacts without interfering with the scaled-down horizontal dimensions, thereby maintaining device density while reducing process integration risks associated with continued miniaturization.
Data Source
AI summary
An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.