Via-Structured RRAM Cells for Scaling Without Voltage Penalty
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Solution Overview
Problem
Conventional RRAM devices face limitations in scaling down due to the dimensions of bottom and top electrode wires, leading to increased resistance and reduced voltage availability, which affects their performance in low-power in-memory computing applications.
Innovation Solution
The fabrication of RRAM devices with a via structure, where the critical device size is defined by the dimension of the filament-forming region within a via, allowing for scaling down using sub-micron lithographic processes, and the filament-forming region is not etched during fabrication to prevent performance deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If electrode wire dimensions are reduced to scale down RRAM devices, then device size is reduced, but resistance increases and operational voltage increases
Solution Approach 1:
The patent transitions from defining device size by two-dimensional electrode wire dimensions to defining it by the one-dimensional via dimension. The via structure allows the critical dimension to be controlled by the via opening size rather than wire width, enabling independent optimization of device footprint and electrical performance. This dimensional shift resolves the contradiction by decoupling device scaling from resistance increase.
Solution Approach 2:
The patent changes the controlling parameter for device size from electrode wire dimensions to via dimension. By making the via dimension the critical size parameter rather than wire width, the device can be scaled down without the resistance penalties that accompany wire dimension reduction. This parameter change enables continued scaling while maintaining low power consumption.
2Volume of moving object
If electrode wire dimensions are reduced to scale down RRAM devices, then device size is reduced, but operational voltage increases
Solution Approach 1:
The patent shifts the size-defining dimension from wire width to via dimension. This allows the device to achieve smaller footprint through via size control while maintaining adequate wire dimensions for low operational voltage. The via-based sizing enables independent optimization of device area and voltage requirements.
Solution Approach 2:
The patent changes the critical size parameter from wire dimension to via dimension. This parameter substitution allows device scaling without the voltage increase that would result from reducing wire dimensions, as the via size controls device identity while wire dimensions can remain optimized for electrical performance.
3Manufacturing precision
If the filament-forming layer is etched to define the device structure, then device geometry is controlled, but performance degradation occurs
Solution Approach 1:
The patent extracts the device geometry definition function from the filament-forming layer etching process and relocates it to the via structure. By using the via opening and isolation layer to define device boundaries, the filament-forming layer can remain intact and unetched, preserving its performance while still achieving precise geometric control through the via-based architecture.
Solution Approach 2:
The patent introduces the via structure and isolation layer as intermediary elements that perform the geometry definition function previously requiring filament-forming layer etching. These intermediaries enable precise device patterning without damaging the filament-forming layer, thus maintaining both manufacturing precision and device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient scaling of RRAM devices and crossbar circuits by reducing the via size, controlling resistance and operation voltage, and maintaining device performance by avoiding etching-induced damage to the filament-forming region.
Implementation Method 1
employing ultra-thin switching metal oxides to form a filament during voltage application
Implementation Method 2
The resistance of the RRAM device may be electrically switched between a high-resistance state (HRS) and a low-resistance state (LRS) by applying suitable programming signals to the RRAM device
Data Source
AI summary
The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating an RRAM device includes: fabricating a first bottom electrode and a second bottom electrode on a substrate; fabricating a first isolation layer on the substrate, the first bottom electrode, and the second bottom electrode; fabricating a via in the first isolation layer to expose a portion of the first bottom electrode; fabricating a switching oxide layer on the first isolation layer and the exposed portion of the first bottom electrode; and fabricating a filament-forming layer by etching a portion of the switching oxide layer that extends beyond the via. The portion of the switching oxide layer does not contact the exposed portion of the first bottom electrode. A top electrode is fabricated on the filament-forming layer. A top metal interconnect may be fabricated on the top electrode and a second isolation layer.