Fully Aligned Via Gapfill Using Ruthenium Capping
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Solution Overview
Problem
Fully aligned vias in semiconductor structures face integration challenges due to void formation in ultra low-k materials, particularly at advanced technology nodes, which is exacerbated by high aspect ratios and time-dependent dielectric breakdown concerns, making it difficult to maintain minimum insulator requirements without compromising electric field integrity.
Innovation Solution
The method involves selectively depositing a capping material on conductive interconnect structures, forming a conformal dielectric layer, and filling the via structure with an alternative metal, using metals like ruthenium (Ru) or cobalt (Co) to relax insulator gapfill requirements and prevent voids, thereby maintaining minimum insulator integrity and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard ULK materials are used to fill topography in fully aligned via structures, then the via structures can be formed, but voids form during deposition and/or curing which prevents proper filling
Solution Approach 1:
The patent changes the material parameter from standard ULK to alternative materials with different physical properties (such as different dielectric constants, viscosities, or curing characteristics). This material substitution allows the filling process to proceed without void formation while maintaining the required electrical insulation properties, directly resolving the contradiction between filling quality and void prevention.
2Ease of manufacture
If the recess depth of fully aligned via structure is reduced to alleviate gapfill problems, then gapfill becomes easier, but minimum insulator requirements are compromised
Solution Approach 1:
Instead of changing the geometric parameter (recess depth), the patent changes the material parameter by substituting alternative insulator materials. These materials have properties that enable them to fill deeper recesses without forming voids, thus maintaining both the required recess depth for electrical isolation and the ease of manufacture for gapfill processes.
3Ease of manufacture
If alternative materials with dielectric constant ≤ 2.7 are used, then gapfill issues are addressed, but the materials may not have satisfactory electrical properties
Solution Approach 1:
The patent carefully selects alternative materials that optimize multiple parameters simultaneously - not just the dielectric constant for gapfill performance, but also electrical properties such as breakdown strength, leakage current characteristics, and compatibility with copper interconnects. This multi-parameter optimization resolves the contradiction between manufacturability and electrical reliability.
4Reliability
If Cu ions diffuse into the dielectric over time, then TDDB occurs and dielectric breakdown happens, but maintaining minimum insulator spacing prevents this
Solution Approach 1:
The patent introduces alternative insulator materials that act as intermediaries between the copper via structures. These materials have superior resistance to Cu ion diffusion and higher breakdown strength, serving as a more effective barrier and mediator that prevents TDDB without requiring increased spacing, thus resolving the contradiction between reliability and device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for relaxed minimum insulator requirements, prevents voids in the insulator material, and reduces via resistance by using selective metals like Ru or Co, enabling higher aspect ratio metal lines and improved electrical performance.
Implementation Method 1
selectively depositing a capping material on a conductive material within a plurality of interconnect structures
Implementation Method 2
selectively depositing a capping material on a conductive material within a plurality of interconnect structures
Implementation Method 3
filling the fully aligned via structure with an alternative metal
Implementation Method 4
filling the fully aligned via structure with an alternative metal
Data Source
AI summary
The present disclosure generally relates to semiconductor structures and, more particularly, to fully aligned via structures having relaxed gapfills and methods of manufacture. The method includes: selectively depositing a capping material on a conductive material within a plurality of interconnect structures to form capped interconnect structures; depositing at least one insulator material over the capped interconnect structures; forming a fully aligned via structure through the at least one insulator material to expose the capping material; filling the fully aligned via structure with an alternative metal; and depositing a metal material on the alternative metal in the fully aligned via structure.