Via Segmentation for Stress Migration Mitigation
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Solution Overview
Problem
Stress migration and electromigration can cause via failures in integrated circuits by accumulating vacancies, leading to increased resistance and potential failure over time, affecting the long-term operation and reliability of the circuit.
Innovation Solution
A geometry-based stress migration model is used to identify high-risk vias, and additional vias are selectively added to reduce the risk of failure due to stress migration and electromigration, by redistributing vacancy regions and attracting vacancies away from critical via interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conductive vias are used to provide electrical connections between metal layers, then the basic electrical connection function is achieved, but stress migration causes vacancy accumulation over time leading to increased resistance and via failure
Solution Approach 1:
The patent divides a single conductive via into multiple smaller vias (via segmentation) or adds redundant vias (via multiplication) to distribute the electrical current and vacancy accumulation risk. This segmentation approach ensures that if one via develops vacancies, the other vias can compensate and maintain electrical connectivity, thereby improving reliability and operational lifetime
Solution Approach 2:
The patent implements preventive measures by designing via structures with built-in redundancy and alternative current paths before stress migration causes failure. The multiple vias are positioned and sized to provide cushioning capacity, allowing the system to withstand vacancy accumulation without immediate failure, thus extending operational lifetime
2Reliability
If additional vias are added to reduce stress migration risk, then via reliability improves, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent applies local quality by selectively adding or modifying vias only in specific high-risk locations identified through stress migration analysis, rather than uniformly increasing via density across the entire device. This targeted approach improves reliability where needed while minimizing overall device complexity
Solution Approach 2:
The patent implements partial action by adding only the necessary number of additional vias to achieve adequate redundancy and stress migration mitigation, rather than adding excessive vias throughout the device. This optimized approach balances reliability improvement with complexity management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the risk of via failure by managing vacancy accumulation and electromigration-induced voids, maintaining acceptable resistance levels and enhancing the reliability and integrity of the integrated circuit.
Implementation Method 1
Conductive vias provide electrical connections between metal layers of an integrated circuit
Implementation Method 2
stress migration can cause the accumulation of vacancies within or at a conductive via, thus increasing the resistance of the conductive via over time
Data Source
AI summary
A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.