Via Structure Mechanical Support via Segmented Dielectric Layers

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Solution Overview

Problem

As semiconductor device sizes decrease, the via structure in interconnection layers is prone to mechanical weakness, leading to a high likelihood of circuit shorts due to insufficient mechanical strength of the dielectric material, which can cause contact with neighboring lower wires.

Innovation Solution

The implementation of a semiconductor device structure that includes a substrate with a first inter-layer dielectric layer, a hard mask layer with specific openings, and a second inter-layer dielectric layer with a trench pattern and via opening, filled by a metal line layer, which provides additional mechanical support and reduces the probability of circuit shorts by maintaining the thickness of the lower metal line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the device size is greatly reduced, then the integration density is improved, but the via structure is prone to mechanical weakness causing circuit shorts

Engineering Contradiction:
Improveintegration densityVSAvoidvia structure mechanical strength
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the dielectric layer into multiple portions: a first dielectric layer, a second dielectric layer, and a third dielectric layer. The via structure extends through these layers at different positions, with each layer providing mechanical support at different heights. This segmentation allows the via to maintain structural integrity while accommodating reduced device dimensions, preventing circuit shorts between adjacent wires.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension solution by forming dielectric layers at different heights (first, second, and third layers). Instead of merely reducing horizontal dimensions for integration, the via structure utilizes vertical stacking to achieve mechanical support. The via extends through multiple vertical layers, providing structural reinforcement without increasing the device footprint, thus maintaining integration density while improving reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of stationary object

If the dielectric material thickness is reduced to maintain device size, then the device dimensions are improved, but the mechanical strength to support the wiring line is insufficient

Engineering Contradiction:
Improvedevice dimensionsVSAvoiddielectric material mechanical strength
Core Design Contradiction:
Length of stationary objectVSStrength

Solution Approach 1:

The dielectric support structure is segmented into three distinct layers positioned at different vertical levels. Each layer contributes to the overall mechanical strength, distributing the support function across multiple segments rather than relying on a single thick layer. This allows the device to maintain compact dimensions while achieving sufficient mechanical strength through the distributed multi-layer structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a composite dielectric structure consisting of multiple dielectric layers (first, second, and third dielectric layers) with potentially different material properties. This composite approach combines the advantages of each layer to provide enhanced mechanical strength and electrical insulation, enabling the device to maintain reduced dimensions while ensuring adequate support for wiring lines and via structures.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS10600732B1Semiconductor device and method for fabricating the same
Publication Date: 2020.03.24 UNITED MICROELECTRONICS CORP
  • US10600732B1 patent drawing
  • US10600732B1 patent drawing
  • US10600732B1 patent drawing

AI summary

A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.