Via with Side Barrier Layer in Encapsulation
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Solution Overview
Problem
Current package-on-package (PoP) configurations are too large and costly, posing challenges for mobile computing devices, and the fabrication process is complex and inefficient.
Innovation Solution
An integrated device with a through encapsulation via (TEV) that includes a side barrier layer, which traverses the encapsulation layer, providing a more compact and cost-effective solution by using a photo-patternable encapsulation layer and a barrier layer to facilitate high-density interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package-on-package (PoP) configuration is used to achieve higher density connections, then connection density is improved, but device size and fabrication complexity increase
Solution Approach 1:
The encapsulation layer is divided into multiple segments: a first portion and a second portion, allowing different regions to serve different functions. This segmentation enables the via structure to traverse through specific portions while maintaining encapsulation integrity in other areas, facilitating high-density interconnects without requiring complete penetration of the encapsulation layer.
Solution Approach 2:
The via structure is configured to traverse the encapsulation layer in a vertical dimension, creating three-dimensional interconnect pathways. This dimensional approach allows connections to be established through the encapsulation layer without increasing the lateral footprint of the device, thereby achieving higher connection density within a compact form factor.
2Volume of moving object
If through encapsulation vias are implemented to reduce device size, then form factor is improved, but manufacturing complexity increases
Solution Approach 1:
The barrier layer is applied selectively to specific portions of the via structure rather than uniformly across the entire via. This local quality approach places the barrier layer only where it is needed to prevent diffusion between the via fill material and the encapsulation layer, simplifying the manufacturing process compared to applying barrier layers to all via surfaces.
Solution Approach 2:
The barrier layer is formed on the via structure before the via is filled with conductive material. This preliminary action prevents diffusion issues during subsequent filling processes and eliminates the need for complex post-fill barrier applications, thereby reducing overall manufacturing complexity.
3Reliability
If barrier layer is added to via structure to prevent diffusion, then reliability is improved, but device complexity increases
Solution Approach 1:
The barrier layer function is extracted and applied only to specific portions of the via structure where diffusion prevention is most critical, rather than applying it to the entire via. This selective approach maintains reliability by preventing diffusion at key interfaces while reducing the overall complexity of the via structure.
Data Source
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Figure 5A
AI summary
Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.