Via Sidewall Encapsulation After Solder Residue Etching
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Solution Overview
Problem
As integrated circuits shrink, the adhesion between via sidewalls and encapsulants in semiconductor devices becomes challenging due to thermal expansion mismatches and solder residue, leading to delamination and visual defects during processing.
Innovation Solution
The use of an encapsulant with low thermal expansion coefficients or low-temperature curing, combined with an etching process to remove solder from via sidewalls, creates a consistent interface and improves adhesion between the via sidewall and the encapsulant, reducing delamination and visual defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional encapsulants with high thermal expansion coefficients are used, then the encapsulation process is straightforward, but delamination occurs between the via sidewall and encapsulant due to thermal expansion mismatch
Solution Approach 1:
The patent applies preliminary action by performing an etching process on the via sidewalls before encapsulation to remove solder residue and create a surface that promotes better adhesion. This preparatory step prevents delamination issues that would occur during subsequent thermal cycling, resolving the contradiction between reliability and processing complexity by addressing the adhesion problem upfront rather than dealing with failures later.
2Reliability
If solder is left on via sidewalls, then the via formation process is complete, but visual defects occur and adhesion to encapsulant deteriorates
Solution Approach 1:
The patent applies the extraction principle by selectively removing solder residue from via sidewalls using an etching process. This extraction of the harmful solder material eliminates the source of visual defects and adhesion problems, while the etching process is designed to remove only the excess solder without damaging the underlying via structure, thus maintaining high processing yield.
3Strength
If high-temperature curing encapsulant is used, then the encapsulant has good mechanical properties, but delamination occurs due to thermal expansion mismatch
Solution Approach 1:
The patent applies parameter changes by modifying the thermal properties of the encapsulant material, specifically selecting materials with lower thermal expansion coefficients that better match the via materials. This parameter change allows the encapsulant to maintain good mechanical properties while reducing thermal expansion mismatch, thereby preventing delamination during high-temperature curing and subsequent thermal cycling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor devices by preventing delamination and voids between the via and encapsulant, while also reducing in-line visual defects and improving processing yields.
Implementation Method 1
the adhesion between via sidewalls and encapsulants in semiconductor devices becomes challenging due to thermal expansion mismatches
Implementation Method 2
an etching process to remove solder from via sidewalls
Data Source
AI summary
Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.