Via Sizing for IR Drop Reduction in IC Power Grids
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Solution Overview
Problem
Integrated circuits experience power loss or voltage drop (IR drop) due to power distribution paths, which adversely affect performance and power efficiency.
Innovation Solution
Increasing the cross-sectional area of conductive paths by substituting smaller vias with larger ones or arrays of vias, and using conductive patches to accommodate larger vias, thereby reducing resistance and minimizing IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If smaller vias are used in power distribution, then device density and integration are improved, but resistance increases and IR drop worsens
Solution Approach 1:
The patent divides a single large via into multiple smaller vias arranged in arrays or grids. This segmentation maintains low resistance by providing multiple parallel current paths while improving device density through better space utilization. The segmented via structures are distributed across the conductive layer to optimize both electrical performance and packing density.
Solution Approach 2:
The patent applies different via sizes, densities, and configurations to different locations within the conductive layer based on local current density requirements. High-current regions receive denser via arrays or larger via structures, while low-current regions use sparser configurations. This localized optimization resolves the contradiction by adapting via characteristics to specific functional requirements rather than using a uniform approach.
2Loss of energy
If via size is increased to reduce resistance, then IR drop is reduced, but available area for other components decreases
Solution Approach 1:
By segmenting a large via into multiple smaller vias, the patent achieves the resistance reduction benefits of larger total via area while preserving more usable space. The distributed arrangement of smaller vias leaves interstitial spaces available for routing other conductors and placing components, thus resolving the area conflict.
Solution Approach 2:
The patent transitions from using single large vias to employing two-dimensional arrays of smaller vias. This dimensional approach allows the via structure to spread out over a larger area with lower local density, reducing the impact on available space while maintaining equivalent or better electrical performance through parallel current paths.
3Loss of energy
If via density is increased to reduce resistance, then power distribution is improved, but manufacturing complexity and design rules become more restrictive
Solution Approach 1:
The patent implements via substitution strategies that are localized to specific regions based on current density analysis. Rather than uniformly increasing via density throughout the entire conductive layer, the invention applies higher via densities only where needed to reduce IR drop, leaving other regions with standard via configurations. This localized approach reduces manufacturing complexity while still achieving power distribution improvements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and efficiency of integrated circuits by reducing voltage drop and improving power distribution, allowing for better utilization of rail voltages in IC devices.
Implementation Method 1
Increasing the cross-sectional area of conductive paths by substituting smaller vias with larger ones or arrays of vias, and using conductive patches to accommodate larger vias, thereby reducing resistance and minimizing IR drop
Data Source
AI summary
A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.