Via Stack Fault Detection in 3D Memory
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Solution Overview
Problem
In three-dimensional memory devices, it is challenging to determine faults in via stacks, particularly when individual connections become inaccessible after stacking and connecting integrated circuit dies through vertical connectors like through-silicon vias, due to issues such as shorted, open, or contaminated connections.
Innovation Solution
A method involving receiver circuits on each die that can selectively ground or supply voltage to the via stack, allowing for the measurement of current and calculation of resistance to detect faults, using either an external or internal connection to apply voltage and measure resulting currents, enabling fault detection even in inaccessible via stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory dies are stacked vertically using through-silicon vias to reduce component size, then memory device density is improved, but fault detection capability deteriorates due to inaccessibility of individual via connections
Solution Approach 1:
The patent divides the via stack into multiple accessible segments by routing separate via stacks to different ball grid array (BGA) locations. This segmentation allows individual via stacks to be tested independently while maintaining high memory density through vertical stacking. The test structure includes multiple via stacks (e.g., first via stack to first BGA, second via stack to second BGA) that can be individually accessed and measured.
Solution Approach 2:
The patent introduces an intermediary test structure consisting of additional vias and BGA connections that provide indirect access to the via stack connections. This intermediary structure enables fault detection without requiring direct physical access to the buried via connections between stacked dies. The intermediary BGA balls serve as access points to measure via stack integrity.
2Reliability
If through-silicon vias are used to connect stacked dies, then electrical communication among dies is improved, but ease of repair deteriorates due to inaccessible via connections
Solution Approach 1:
The patent segments the via stack connections into multiple independently accessible groups, each routed to separate BGA locations. This allows individual via stacks to be tested and potentially replaced without affecting other via stacks. The segmentation enables targeted repair efforts on specific failed via stacks while leaving functional stacks intact.
Solution Approach 2:
The patent creates redundant via stack paths that can serve as backups. By having multiple via stacks connecting similar functional blocks (e.g., multiple via stacks between memory dies), if one via stack fails, alternative via stacks can be used. The test structure identifies failed via stacks so they can be replaced or bypassed using redundant paths.
3Device complexity
If vias extend through the thickness of multiple dies to provide vertical connections, then device integration is improved, but manufacturing precision requirements worsen due to alignment complexity
Solution Approach 1:
The patent divides the via stack formation into multiple discrete manufacturing steps, with each via stack being formed and aligned independently. This segmentation allows for better control of alignment precision in each step rather than attempting to align all vias in a single complex operation. Each via stack can be formed with its own alignment references to the BGA locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective detection of faults in via stacks, such as shorted or open connections, by calculating resistance or measuring current, allowing for identification of defects within the stacked connections without requiring external access.
Implementation Method 1
A method involves a receiver circuit of a memory device selectively grounding or supplying voltage to a via stack of a memory device
Implementation Method 2
allowing for the measurement of current and calculation of resistance to detect faults
Data Source
AI summary
A method and apparatus are disclosed. One such method includes selecting a die of a plurality of dies that are coupled together through a via stack. A via on the selected die can be coupled to ground. A supply voltage is coupled to an end of the via stack and a resulting current measured. A calculated resistance is compared to an expected resistance to determine if a fault exists in the via stack.