Constrained Via Stack Layout for Crack-Resistant Silicon Nodes
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Solution Overview
Problem
The unconstrained via stacking configuration in semiconductor devices leads to via cracks and delamination, particularly in advanced silicon node products, due to non-uniform via stress sensitivity and thermal expansion, which is exacerbated by high pulling forces during thermal cycling.
Innovation Solution
Implementing a constrained via stacking configuration with specific constraints on the number and arrangement of vias, such as limiting the number of first vias to be less than or equal to the number of second vias, and ensuring no more than three second vias, to mitigate via cracks and delamination in dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If unconstrained via stacking configuration is used, then manufacturing flexibility is improved, but via cracks and delamination occur due to non-uniform stress and thermal expansion
Solution Approach 1:
The patent applies parameter changes by imposing specific constraints on via stacking configuration parameters. The number of first vias is limited to be less than or equal to the number of second vias, and the number of second vias is limited to no more than three. These parameter constraints optimize the via arrangement to achieve uniform stress distribution and thermal expansion characteristics, preventing via cracks and delamination while maintaining manufacturing flexibility.
Solution Approach 2:
The patent applies local quality by creating different via stacking configurations in different regions of the dielectric layer stack. By controlling the number and arrangement of vias locally (with specific limits on first and second vias), the patent achieves uniform stress and thermal expansion properties in critical areas, thereby preventing reliability issues while allowing flexibility in other regions.
2Duration of action of moving object
If high pulling forces are applied during thermal cycling, then device operation is maintained, but via cracks and delamination are exacerbated
Solution Approach 1:
The patent applies preliminary anti-action by pre-constraining the via stacking configuration before thermal cycling occurs. By limiting the number of first vias to be less than or equal to second vias, and second vias to no more than three, the patent creates a stress-distributing structure that counteracts the high pulling forces during thermal cycling, preventing via cracks and delamination from occurring in the first place.
3Reliability
If via stacking configuration is constrained, then via crack and delamination are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent simplifies the constrained configuration by defining clear parameter rules: the number of first vias must be less than or equal to the number of second vias, and the number of second vias must be no more than three. These straightforward parameter constraints make the complex via arrangement manageable and manufacturable while still achieving the reliability benefit of reduced via cracks and delamination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The constrained via configuration effectively reduces via cracks and delamination, enhancing the manufacturing yield and reliability of semiconductor devices, especially in advanced silicon node products.
Implementation Method 1
via cracks and delamination, particularly in advanced silicon node products, due to non-uniform via stress sensitivity and thermal expansion
Data Source
AI summary
An electrical connection structure includes a dielectric layer stack of a plurality of dielectric layers including a first dielectric layer as an uppermost layer, and a second dielectric layer under the first dielectric layer, a plurality of metal layers in the plurality of dielectric layers, a via stack in the plurality of dielectric layers that connects the plurality of metal layers, an upper metal layer on the dielectric layer stack over the via stack, and an upper dielectric layer on the dielectric layer stack and including an upper dielectric layer opening over the upper metal layer and the via stack. A number of first vias in the first dielectric layer, may be less than or equal to a number of second vias in the second dielectric layer, and the number of second vias in the second dielectric layer may be less than or equal to 3.