MRAM Integration via Via-Stacked MTJ Structures for 30nm CMOS
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Solution Overview
Problem
The fabrication of magnetic tunneling junctions (MTJ) in embedded magnetoresistive random-access memory (MRAM) devices faces challenges in process margin and device performance due to the limited vertical spacing between metal lines, leading to restricted MTJ thickness and increased risk of electrical shorts during etching and chemical mechanical polishing (CMP) processes.
Innovation Solution
The method involves fabricating MTJ structures between two layers of metal vias instead of metal lines, allowing for a thicker MTJ hard mask and top electrode, reducing manufacturing costs, and enabling greater over etch to minimize conductive metal re-deposition on the MTJ sidewalls, thus eliminating electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MTJ is formed between two metal lines with limited vertical spacing, then device integration is achieved, but the MTJ thickness is restricted and process margin is reduced
Solution Approach 1:
The patent transitions from planar MTJ formation between metal lines to vertical MTJ formation between metal vias. By utilizing the vertical dimension and stacking MTJ structures between via electrodes at different metal layers, the invention overcomes the limited lateral spacing constraint while maintaining compatibility with advanced CMOS node pitch requirements
Solution Approach 2:
The patent divides the interconnect structure into segmented via electrodes that serve as discrete bottom and top electrodes for the MTJ. This segmentation allows independent optimization of via dimensions and spacing, enabling sufficient vertical clearance for thicker MTJ structures while maintaining horizontal pitch compatibility
2Reliability
If MTJ over etch is performed to remove metal re-deposition, then electrical shorts are prevented, but device performance may be compromised when via height is limited
Solution Approach 1:
The patent designs the via structure with sufficient vertical height and appropriate aspect ratio beforehand to accommodate the required MTJ over etch margin. This prior cushioning in the via dimension allows aggressive over etch to remove conductive metal re-deposition from sidewalls while maintaining control over etch depth to prevent damage to the MTJ active region
3Adaptability or versatility
If MTJ hard mask and top electrode thickness is reduced to fit limited spacing, then integration is enabled, but later CMP and etch processes are compromised
Solution Approach 1:
The patent relocates the MTJ structure from a lateral configuration to a vertical configuration between via electrodes. This dimensional change provides sufficient vertical spacing to accommodate thicker hard mask and top electrode layers, enabling robust chemical mechanical polishing (CMP) and etch processes while maintaining integration with the CMOS interconnect architecture
Data Source
AI summary
A complementary metal oxide semiconductor (CMOS) device comprises a first metal line, a first metal via on the first metal line, a magnetic tunneling junction (MTJ) device on the first metal via wherein the first metal via acts as a bottom electrode for the MTJ device, a second metal via on the MTJ device, and a second metal line on the second metal via.