Redistribution Substrate Via Stacking for Reliable Chip Pad Contacts
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high reliability due to spatial limitations and the need for precise line-width reduction in forming redistribution lines, which requires high accuracy and can be complicated by the requirement for fine patterning processes.
Innovation Solution
The semiconductor package design incorporates a redistribution substrate with stacked via structures where the second via part is in contact with the chip pad without overlapping the first via part, reducing the contact area and eliminating the need for fine patterning, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redistribution lines are formed with overlapping via structures, then electrical connection is achieved, but manufacturing precision requirements increase due to the need for fine patterning and line-width reduction
Solution Approach 1:
The patent transitions from a planar overlapping via structure to a stacked via structure where vias are arranged in vertical layers. The first via part contacts the chip pad at a lower level, while the second via part extends upward to contact the redistribution pattern, eliminating the need for fine lateral patterning and reducing manufacturing precision requirements.
Solution Approach 2:
The via structure is segmented into multiple independent parts (first via part and second via part) that can be formed separately and stacked vertically. This segmentation allows each via part to be optimized independently and reduces the complexity of forming a single continuous via through fine patterning.
2Manufacturing precision
If fine patterning processes are used to achieve precise line-width reduction, then redistribution line accuracy is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent resolves the complexity of fine patterning by moving the precision requirement from the lateral dimension to the vertical dimension. Instead of requiring precise lateral alignment for line-width reduction, the stacked via structure uses vertical stacking to achieve accurate electrical connections, simplifying the patterning process.
Solution Approach 2:
The first via part is formed and contacted with the chip pad before forming the second via part. This preliminary action allows the redistribution pattern to be established in a controlled sequence, reducing the need for complex simultaneous patterning operations.
3Area of stationary object
If via structures are stacked with vertical overlap, then space utilization is improved, but contact area between metallic and dielectric materials increases leading to potential reliability issues
Solution Approach 1:
The via structure is divided into separate first and second via parts with distinct contact points. The first via part contacts the chip pad while the second via part contacts the redistribution pattern, creating discrete contact areas that minimize unnecessary metallic-dielectric interfaces and improve reliability.
Solution Approach 2:
The patent uses vertical stacking to achieve space-efficient layout while controlling the lateral footprint. The stacked via structure utilizes the vertical dimension for routing, allowing compact substrate design without increasing the contact area between metallic materials and dielectric materials at any single level.
Data Source
AI summary
Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.