Via Redundancy for Stress Migration Reliability
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Solution Overview
Problem
Stress migration and electromigration can cause via failures in integrated circuits by accumulating vacancies, leading to increased resistance and potential failure over time, affecting the long-term operation and reliability of the circuit.
Innovation Solution
A geometry-based stress migration model is used to identify high-risk vias, and additional vias are selectively added to reduce the risk of failure due to stress migration and electromigration, by redistributing vacancy regions and attracting vacancies away from critical via boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conductive vias are used to provide electrical connections between metal layers, then the circuit can be manufactured with standard processes, but stress migration over time causes vacancy accumulation leading to via failure
Solution Approach 1:
The patent performs preliminary stress migration analysis using a geometry-based model to identify high-risk vias before finalizing the circuit design. Additional vias are proactively added to redistribute vacancy regions and prevent future failure, rather than waiting for actual via failures to occur during operation.
Solution Approach 2:
The patent converts the harmful stress migration effect into a beneficial design tool by using vacancy region analysis to guide via placement. The same physical mechanism that causes failure (stress migration and vacancy accumulation) is used predictively to identify vulnerable areas and strengthen the design against it.
2Reliability
If additional vias are added to reduce stress migration risk, then via reliability improves, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent applies local quality by adding via structures only in specific high-risk locations identified through stress migration analysis, rather than uniformly increasing via density across the entire circuit. The geometry-based model evaluates vacancy region characteristics for each via location to determine where additional vias are necessary.
Solution Approach 2:
The patent changes the geometric parameters of the via structure by adjusting via dimensions and spacing based on the stress migration model results. The via geometry is optimized to redistribute vacancy regions while maintaining electrical performance requirements.
3Reliability
If via density is increased to prevent vacancy accumulation, then stress migration resistance improves, but manufacturing precision requirements increase
Solution Approach 1:
The stress migration analysis and via optimization are performed during the design stage before manufacturing, allowing precise via placement to be built into the fabrication process. The geometry-based model provides specific via location and dimension recommendations that can be directly implemented in the manufacturing process.
Solution Approach 2:
The patent uses the stress migration model to create an optimized via layout that copies and redistributes vacancy regions across the circuit. The model serves as a template for via placement, ensuring that each via is positioned to maximize its effectiveness in preventing stress migration while maintaining manufacturability.
Data Source
AI summary
A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.