Redistribution Layer Via Structure for High-Density Fan-Out Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and miniaturization of semiconductor devices due to limitations in bonding processes and packaging techniques, which hinder further reductions in physical size and improvements in performance.
Innovation Solution
The development of an ultra-high density redistribution layer interconnect for integrated fan-out (InFO) packages, utilizing a polymer layer for protection, die attach films, and advanced metallization processes to form vias and metallization layers, allowing for the stacking and bonding of semiconductor devices with improved electrical connectivity and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bonding processes are used to stack semiconductor devices, then integration density is improved, but device complexity and process sophistication increase
Solution Approach 1:
The patent divides the semiconductor device into multiple separate substrates (first substrate and second substrate) that are bonded together. This segmentation allows independent fabrication and optimization of each substrate while achieving high integration density through stacking, thereby managing complexity by modularizing the device structure.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by bonding multiple substrates vertically. This dimensional change enables higher integration density without further reducing feature size, and the standardized bonding interface simplifies the overall process complexity despite the increased vertical integration.
2Quantity of substance
If feature size is reduced to increase integration density, then component quantity increases, but manufacturing precision requirements worsen
Solution Approach 1:
The patent moves from two-dimensional planar integration to three-dimensional vertical stacking. This allows integration density to increase through the third dimension (stacking multiple substrates) rather than continuously reducing feature size, thereby relaxing manufacturing precision requirements while still achieving higher component quantity.
Solution Approach 2:
By segmenting the device into multiple substrates with standard-sized features that are bonded together, the patent avoids the need to miniaturize every feature across the entire device. Each substrate can be fabricated with relaxed precision requirements, and the bonding process integrates them into a high-density configuration.
3Volume of moving object
If stacked and bonded semiconductor devices are used, then physical size is reduced, but bonding process sophistication increases
Solution Approach 1:
The patent segments the semiconductor device into multiple substrates that can be fabricated separately using standard processes and then bonded together. This segmentation enables physical size reduction through vertical stacking while managing bonding complexity by using standardized, modular interfaces between substrates.
Solution Approach 2:
The bonding interface is designed to be universal and standardized, allowing the same bonding process to be applied repeatedly across multiple substrate interfaces. This multi-functionality reduces the sophistication required for each individual bonding step, as the process is standardized and can be automated.
Data Source
AI summary
In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.