Via Structure Sandwich Design for Stress Management
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Solution Overview
Problem
Existing via structures in semiconductor devices face issues due to unevenly distributed stress caused by differences in mechanical properties and coefficients of thermal expansion between different filling materials, leading to potential cracks within the devices.
Innovation Solution
The implementation of sandwich structures comprising an insulating layer, a conductive layer, and additional insulating layers within the via structures, with specific layer configurations and processing steps such as planarization and grinding to manage stress and ensure electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional filling materials are used in via structures, then the via can be formed and provide electrical connectivity, but unevenly distributed stress occurs due to differences in mechanical properties and coefficients of thermal expansion, leading to potential cracks
Solution Approach 1:
The patent applies composite materials by combining multiple filling materials with different mechanical properties and coefficients of thermal expansion within the same via structure. Specifically, different portions of the via are filled with different materials (e.g., conductive material in some regions, insulating material in others) to create a composite structure that balances stress distribution and prevents cracks while maintaining electrical connectivity where needed.
2Productivity
If through silicon via technology is used to replace traditional metal wires, then chip stacking density increases and signal transmission speeds improve, but stress concentration occurs due to material property differences
Solution Approach 1:
The patent applies local quality by assigning different material properties to different regions within the via structure. Specifically, conductive filling materials are placed in regions requiring electrical connectivity while insulating filling materials are placed in regions where electrical isolation is needed. This localized differentiation allows the structure to maintain high chip stacking density while reducing stress concentration through appropriate material selection in stress-critical areas.
Data Source
AI summary
A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a bottom metal layer and another electronic component below the via structure. The via structure includes a through hole penetrating from a first surface to an opposite second surface of a substrate, a filling insulating layer within the through hole, a first conductive layer, which is within the through hole and surrounds the filling insulating layer, wherein a portion of the first conductive layer is below the filling insulating layer and at the bottom of the through hole. The via structure further includes a first insulating layer, which is on the sidewalls of the through hole and surrounds the first conductive layer.