Through-Memory-Level Via Structures for 3D Memory Integration
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Solution Overview
Problem
As three-dimensional memory devices scale to smaller dimensions, the device area for peripheral devices becomes significant, necessitating a method to integrate peripheral devices like word line driver circuits without increasing the chip size and to enhance power distribution efficiently.
Innovation Solution
The implementation of through-memory-level via structures that extend from the topmost surface to the bottommost surface of the memory-level assembly, allowing for the integration of peripheral devices and improved power distribution within a compact semiconductor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory devices scale to smaller device dimensions, then storage density is improved, but the device area for peripheral devices takes up a significant portion of the total chip area
Solution Approach 1:
The patent implements through-memory-level via structures that extend vertically through multiple alternating stacks, utilizing the vertical dimension to connect peripheral devices across different memory levels. This allows peripheral devices to be integrated in the vertical space above the memory array rather than consuming additional horizontal chip area, thereby maintaining high storage density while accommodating peripheral circuits.
2Area of stationary object
If peripheral devices are integrated without increasing chip size, then chip area is reduced, but device complexity increases
Solution Approach 1:
The through-memory-level via structures serve multiple functions simultaneously: they provide vertical interconnects for peripheral devices, enable power distribution across memory levels, and act as structural support elements. This multi-functionality reduces the need for separate dedicated structures, thereby integrating peripheral devices without proportionally increasing device complexity.
3Power
If power distribution is enhanced, then performance is improved, but chip footprint increases
Solution Approach 1:
The patent utilizes the vertical dimension by implementing through-memory-level via structures that extend through multiple alternating stacks. These vertical interconnects provide efficient power distribution pathways from lower to upper memory levels without requiring additional horizontal space, thereby enhancing power distribution while maintaining a compact chip footprint.
Data Source
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Figure 2A
AI summary
Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.