Through-Memory-Level Via Structures for 3D NAND Integration
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Solution Overview
Problem
As three-dimensional memory devices scale to smaller dimensions, the device area for peripheral devices becomes significant, necessitating a method to incorporate word line driver circuits without increasing the total chip size and to enhance power distribution efficiently.
Innovation Solution
The development of a semiconductor structure that includes a monolithic three-dimensional NAND string memory device with through-memory-level via structures and alternating stacks of insulating and sacrificial material layers, allowing for the integration of peripheral devices and efficient power distribution within a compact chip footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory devices scale to smaller dimensions, then storage density is improved, but the device area for peripheral devices becomes significant relative to total chip area
Solution Approach 1:
The patent implements through-memory-level via structures that extend vertically through multiple memory levels (first memory level, second memory level, third memory level) to reach peripheral devices. This vertical interconnection approach moves data and power pathways from the horizontal plane to the vertical dimension, allowing peripheral devices to be positioned at the bottom of the stack while maintaining efficient connectivity without consuming additional lateral chip area.
2Adaptability or versatility
If peripheral devices are integrated into three-dimensional memory devices, then functionality is improved, but chip size increases
Solution Approach 1:
The patent embeds peripheral devices within the three-dimensional memory stack structure itself, nesting them at the bottom level beneath the memory levels. The through-memory-level via structures are nested within the vertical stack, passing through multiple memory levels to connect to the peripheral devices. This nesting approach integrates additional functionality without increasing the lateral footprint of the chip.
Solution Approach 2:
Peripheral devices are positioned in the vertical dimension at the bottom of the stack rather than being placed in the lateral plane. The through-memory-level via structures provide vertical interconnection pathways, enabling peripheral devices to be integrated into the three-dimensional architecture without consuming additional horizontal chip area.
3Power
If power distribution network is enhanced in three-dimensional memory devices, then performance is improved, but chip footprint increases
Solution Approach 1:
The patent implements vertical power distribution pathways through the through-memory-level via structures that extend from the bottom peripheral devices through multiple memory levels. This vertical power delivery approach consolidates power distribution into the third dimension, reducing the need for extensive lateral power routing networks and minimizing the chip footprint while maintaining efficient power delivery to all memory elements.
Data Source
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AI summary
A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.