Via-Integrated Substrate Packaging With Embedded Passives
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Solution Overview
Problem
Conventional electronic packages and manufacturing methods result in excessive costs, decreased reliability, and large package sizes with relatively low performance.
Innovation Solution
The development of an electronic device with a substrate having conductive vias and embedded conductors and dielectric structures on both sides, including passive components like capacitors and inductors, which are integrated to provide improved electrical coupling and protection, and a method for manufacturing this device involving thinning processes and precise layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional electronic packages are used, then manufacturing is simpler, but device size is too large and performance is low
Solution Approach 1:
The patent transitions from planar 2D packaging to three-dimensional stacked packaging, where multiple die layers are vertically stacked and interconnected through through-silicon vias (TSVs). This dimensional change enables higher device integration density, reducing the footprint area while maintaining manufacturing feasibility through established semiconductor fabrication processes adapted for 3D stacking.
Solution Approach 2:
The patent implements nested packaging by placing multiple functional die layers (RF die, base die, antenna die) within a single package substrate structure. Each die is embedded in recesses of the substrate, with interconnect structures nested between layers. This nesting approach consolidates multiple components into one compact package, reducing overall device size while maintaining manufacturing simplicity through modular assembly.
2Reliability
If conventional packaging methods are used, then manufacturing cost is lower, but reliability is decreased
Solution Approach 1:
The patent incorporates preliminary protective measures by forming conformal dielectric layers and conductive plugs during the fabrication process before final assembly. Through-silicon vias are pre-formed with protective liners, and dielectric materials are deposited in advance to provide mechanical support and electrical isolation. These preliminary actions enhance reliability by preventing defects during subsequent handling and assembly operations.
Solution Approach 2:
The patent provides beforehand protection by embedding die in conformal dielectric structures that cushion and protect fragile semiconductor die during assembly and operation. The dielectric material surrounding each die acts as a protective cushion against mechanical stress, thermal expansion, and electrical interference, thereby improving reliability without significantly complicating the manufacturing process.
3Reliability
If conventional packages are used, then manufacturing is easier, but performance is relatively low
Solution Approach 1:
The patent introduces intermediary conductive structures, including through-silicon vias and conductive plugs, that mediate electrical connections between stacked die layers. These intermediary elements provide controlled impedance pathways and reliable electrical coupling between RF die, base die, and antenna die, improving signal integrity and electrical performance while maintaining a manageable structural complexity through systematic via formation processes.
4Volume of moving object
If larger package sizes are used, then manufacturing is simpler, but device performance is reduced
Solution Approach 1:
The patent applies local quality optimization by configuring inductor structures with specific geometric parameters (trace width, spacing, number of turns) tailored to achieve desired inductance values within the compact 3D package. Different regions of the package substrate are designed with localized inductor patterns optimized for their specific electrical functions, enabling high-performance passive components in a reduced package volume without compromising manufacturing simplicity.
Data Source
AI summary
In one example, an electronic device includes a substrate with a substrate front side, a substrate rear side opposite to the substrate front side, a substrate body, and conductive vias extending through the substrate body from the substrate front side to the substrate rear side. A first construct is over the substrate front side and includes a first dielectric structure and first conductors embedded in the first dielectric structure and coupled to the conductive vias. A second construct is over the substrate rear side and includes a second dielectric structure and second conductors embedded in the second dielectric structure and coupled to the conductive vias. One or more of the first conductors or the second conductors define one or more passive devices. Other examples and related methods are also disclosed herein.