Via Test Structure for High-Sensitivity Resistance Measurement
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Solution Overview
Problem
Integrated circuits face challenges in detecting and characterizing process-related errors in vias, which can lead to significant yield loss due to low error rates in semiconductor fabrication, as existing measurement methods fail to reliably identify weak vias and extrinsic error sources in the final product.
Innovation Solution
A test structure or test chip with a plurality of individually addressable vias is created, allowing for high-sensitivity detection and characterization of deviations in via fabrication, using a 4-terminal measurement method to assess resistance and drift, and simulating process variations to design in expected layout modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional measurement methods are used to detect via errors, then the measurement process is simple, but the measurement precision is insufficient to reliably identify weak vias and extrinsic error sources
Solution Approach 1:
The measurement system is segmented into multiple independent test structures, each designed to detect specific types of via errors. Individual vias are measured separately using a 4-terminal method, allowing precise identification of weak vias without interference from neighboring structures. This segmentation enables high detection sensitivity while keeping each measurement operation relatively simple.
Solution Approach 2:
A dedicated test structure with addressable vias serves as an intermediary between the measurement system and the actual via errors. This test structure includes control circuits that enable selective activation and measurement of individual vias, acting as a mediator that translates complex via error detection into manageable measurement steps.
2Reliability
If individual via measurement is implemented, then the detection reliability improves, but the manufacturing complexity increases
Solution Approach 1:
Test structures with predetermined via configurations are fabricated in advance as part of the standard manufacturing process. These pre-designed test structures include addressable vias and control circuits that are integrated into the chip before final assembly. This preliminary action allows individual via measurement capability to be built-in without adding complexity to the main product fabrication.
Solution Approach 2:
The test structures are designed to be universal and can be applied to various via types and configurations. The same measurement approach can detect different error modes (open circuits, high resistance, drift) across multiple via locations. This multi-functionality reduces the need for separate measurement systems for different via types, simplifying the overall manufacturing process.
3Productivity
If process variations are simulated to identify failure modes, then the manufacturing optimization improves, but the testing time increases
Solution Approach 1:
The measurement system uses periodic scanning of via parameters to detect drift and degradation over time. By measuring vias at multiple time points during the manufacturing process, the system can identify failure modes and process variations efficiently. This periodic measurement approach provides comprehensive data for manufacturing optimization without requiring continuous monitoring that would consume excessive time.
Solution Approach 2:
Failure modes are identified through preliminary testing of test structures before full production. By simulating process variations on test chips first, the measurement system can be calibrated and failure patterns can be characterized in advance. This preliminary characterization reduces the time needed for actual production testing while maintaining high manufacturing optimization capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables early identification of failure modes, accurate assessment of error rates, and optimization of the manufacturing process by simulating critical parameter variations, thereby improving yield and reducing costs associated with defective components.
Implementation Method 1
using a 4-terminal measurement method to assess resistance and drift
Data Source
AI summary
An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.