Via-Trace Structures with Subtractive Etch Lithography
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Solution Overview
Problem
Conventional package substrate manufacturing techniques are limited in reducing feature size while maintaining accuracy, often requiring costly materials and being constrained by alignment errors, which restrict the formation of smaller and more accurately aligned vias and traces.
Innovation Solution
The development of via-trace structures with improved alignment, utilizing standard lithography tools and commercially available materials, through a subtractive etch patterned zero misalignment lithography process that allows for the formation of smaller features with reduced alignment offsets, using a single mask to pattern conductive pathways in package substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional lithography techniques are used to reduce feature size, then feature size decreases, but alignment accuracy deteriorates due to alignment errors between multiple masks
Solution Approach 1:
The patent combines the patterning of vias and traces into a single lithography step using one mask, eliminating the need for separate alignment steps. This merging of operations allows smaller features to be formed without the alignment errors that accumulate when using multiple masks, directly resolving the contradiction between reducing feature size and maintaining alignment accuracy.
2Adaptability or versatility
If multiple masks are used to pattern different features, then feature complexity increases, but alignment error accumulates
Solution Approach 1:
The single mask design integrates multiple feature patterns (vias and traces) that would traditionally require separate masks. This consolidation maintains the ability to create complex interconnect structures while eliminating alignment errors between masks, as all features are patterned simultaneously in one lithography exposure step.
Data Source
AI summary
Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.