Via-Based Transistor Interconnect Eliminates Wire Bonds
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Solution Overview
Problem
Existing electronic devices face design limitations due to the need for wire bonds to connect semiconductor chips, which restricts chip size and increases space consumption, hindering compact design and efficient heat dissipation.
Innovation Solution
The implementation of a via connection between transistor terminals of semiconductor chips, allowing direct electrical coupling without wire bonds, enabling a substrate that extends beyond chip edges and providing increased design freedom and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonds are used to connect transistor terminals of semiconductor chips to substrates, then electrical connection is achieved, but space consumption increases and design freedom is restricted
Solution Approach 1:
The patent extracts and eliminates the wire bond from the conventional connection structure. Instead of using separate wire bonds to connect transistor terminals to substrates, the invention integrates the electrical connection directly into the substrate through vias that contact the transistor terminals at the chip edges, thereby removing the space-consuming wire bonds while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from a planar wire bond connection to a vertical via-based connection. The electrical connection is achieved by forming vias in the substrate that extend downward to contact the transistor terminals at the chip edges, utilizing the vertical dimension rather than lateral wire bonds, thus reducing the horizontal space consumption.
2Reliability
If wire bonds are used for connecting transistor terminals, then electrical coupling is established, but chip size is restricted and heat dissipation efficiency decreases
Solution Approach 1:
The invention removes the wire bond constraint that limits chip size. By eliminating the need for wire bonds and their associated clearance requirements, the substrate can extend directly over the entire chip surface, allowing larger chip dimensions and improved adaptability for different power dissipation requirements.
Solution Approach 2:
Instead of having the substrate connect to transistor terminals through lateral wire bonds, the invention inverts the connection approach by having the substrate extend over the chip and connect vertically through vias to the terminals at the chip edges. This inversion allows the substrate to fully cover the chip area, enabling larger chip sizes.
3Reliability
If substrate is constrained to not extend beyond chip edges, then wire bond clearance is maintained, but design freedom and heat dissipation capability are reduced
Solution Approach 1:
The patent removes wire bonds from the system, thereby eliminating the clearance requirement between substrate and wire bonds. This allows the substrate to extend freely beyond the chip edges and fully cover the chip surface, maximizing design freedom and heat dissipation capability without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces space consumption, allows for a compact design, and enhances heat dissipation by enabling a larger chip size and efficient thermal management, while eliminating the need for wire bonds.
Implementation Method 1
a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface
Implementation Method 2
a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate
Data Source
AI summary
An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.