Buried Interconnect Via-Trench Layout for Low-Capacitance Contacts
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Solution Overview
Problem
As semiconductor devices become more highly integrated, the resistance of metal lines and contact resistance increase due to decreasing width and contact area, while parasitic capacitance rises with the narrowing distance between metal lines and contact plugs.
Innovation Solution
A method for fabricating semiconductor devices that involves forming a dielectric layer over a substrate, creating hole-shaped partial vias and line-shaped trenches with specific dimensions, and gap-filling these structures with a conductive material to bury metal lines while minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width and contact area of metal line are decreased to achieve high integration, then the integration density is improved, but the resistance of metal line and contact resistance increase
Solution Approach 1:
The patent applies nesting by placing a via inside a trench structure. The via is formed within the trench region, creating a nested configuration where the conductive via is surrounded by the conductive trench material. This nested structure increases the effective contact area and conductive path without increasing the overall footprint, thereby maintaining low resistance while achieving high integration density.
2Productivity
If the distance between metal line and contact plugs is narrowed to achieve high integration, then the integration density is improved, but the parasitic capacitance increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical structure by forming trenches that extend vertically and creating vias within these trenches. This dimensional change allows contact plugs to be positioned in the vertical dimension rather than only in the horizontal plane, reducing parasitic capacitance between metal lines and contact plugs while maintaining high integration density through vertical stacking.
3Manufacturing precision
If the aspect ratio of vias is reduced to improve gap-fill margins, then the void formation is reduced, but the contact area between vias and metal lines decreases
Solution Approach 1:
The patent merges the via and trench structures into a unified conductive contact system. The via and trench are both filled with conductive material to form an integrated contact structure that combines the benefits of both geometries. This merged structure maintains a low aspect ratio for improved gap-fill while preserving adequate contact area through the combined volume of the via and trench regions.
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a dielectric layer over a substrate; forming a hole-shaped partial via in the dielectric layer; forming a line-shaped trench that partially overlaps with the partial via and has a greater line width than a line width of the partial via in the dielectric layer; forming a hole-shaped via that has a smaller line width than the line width of the partial via and penetrates the dielectric layer on a lower surface of the partial via; and gap-filling the via, the partial via and the trench with a conductive material, wherein a lower surface of the trench is positioned at a higher level than the lower surface of the partial via.