Simultaneous Via and Trench Patterning via Etch Rate Control
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Solution Overview
Problem
The semiconductor industry faces complexity and high costs in fabricating modern integrated chips due to the need for multiple lithography masks and processing steps to form metal and via levels, especially as feature sizes approach the limit of current illumination wavelengths, making it challenging to scale down further.
Innovation Solution
A photolithography mask is designed to form both metal and via levels within a single inter-level dielectric layer using a single lithography and etch step, leveraging the difference in critical dimensions between via and metal features to control etch rates, allowing for simultaneous formation of both levels without inter-level dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate lithography and etch steps are used for metal and via levels, then manufacturing precision is maintained, but device complexity and processing time increase
Solution Approach 1:
The patent combines the formation of metal levels and via levels into a single dual-patterning lithography and etch process. By using a first photoresist material for metal level patterning and a second photoresist material for via level patterning simultaneously, the process eliminates separate lithography and etch steps, reducing device complexity while maintaining manufacturing precision through the use of different etch rates for each feature type.
Solution Approach 2:
The patent creates a universal processing step that forms both metal and via levels in a single operation. The dual-patterning approach allows one lithography and etch cycle to perform multiple functions: defining metal trench patterns, defining via hole patterns, and creating the necessary depth differences between metal and via features through selective etching, thereby reducing overall process complexity.
2Productivity
If feature sizes are reduced to increase device density, then productivity improves, but manufacturing precision deteriorates due to illumination wavelength limits
Solution Approach 1:
The patent segments the patterning process into two distinct photoresist material systems: a first photoresist material with higher sensitivity for defining metal trench patterns, and a second photoresist material with lower sensitivity for defining via hole patterns. This segmentation allows each material to be optimized for its specific feature type, enabling precise control of small features while maintaining the ability to form larger features in the same lithography step.
Solution Approach 2:
The patent applies local quality by using different photoresist materials with different sensitivities in different spatial locations on the same wafer. The first photoresist material is applied in regions where metal trenches are to be formed, while the second photoresist material is applied in regions where via holes are to be formed. This allows each region to have the optimal photoresist properties for its intended feature size, enabling high device density while maintaining manufacturing precision.
3Ease of manufacture
If single lithography and etch step is used to reduce processing complexity, then ease of manufacture improves, but reliability may deteriorate due to potential inter-level dielectric breakdown
Solution Approach 1:
The patent utilizes parameter changes by exploiting the different etch rates of the inter-level dielectric material when exposed to different photoresist materials. The first photoresist material (higher sensitivity) creates a faster etch rate for metal trench formation, while the second photoresist material (lower sensitivity) creates a slower etch rate for via hole formation. This parameter differentiation allows the single etch step to create the necessary depth variations without compromising inter-level dielectric integrity, as each feature type is etched to the appropriate depth through controlled etch rate modulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing complexity and costs by eliminating the need for separate photolithography and etch steps for metal and via levels, enabling efficient formation of multiple design levels with improved reliability and preventing inter-level dielectric breakdown.
Implementation Method 1
The first critical dimension is larger than the second critical dimension thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings
Data Source
AI summary
One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.