Redirecting Void Diffusion Away from Vias in Integrated Circuits
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Solution Overview
Problem
Stress-induced voids in integrated circuits, particularly at vias, lead to circuit failures due to copper atom diffusion along tensile stress gradients, which existing technologies fail to adequately address, resulting in increased manufacturing costs and reduced reliability.
Innovation Solution
The solution involves forming an electrical conductor with a via and either adding an electrically conductive area or removing a portion of the dielectric layer adjacent to the conductor to divert void diffusion away from the via, thereby reducing tensile stress and preventing void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via formation is used in integrated circuits, then manufacturing process is simple, but void diffusion occurs at vias leading to circuit failures
Solution Approach 1:
The patent divides the conductor structure into multiple segments: the original via, additional via structures, and stress relief features. This segmentation allows each component to address specific aspects of void diffusion independently, improving overall via reliability without requiring complete redesign of the entire interconnect structure.
Solution Approach 2:
The patent implements preliminary stress management by forming stress relief features and additional conductor structures before void diffusion can occur. This proactive approach prevents void accumulation at critical via locations by establishing stress distribution patterns that redirect void diffusion away from original vias during subsequent manufacturing and operation.
2Reliability
If additional vias or interconnect layers are added to address void diffusion, then via reliability improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges multiple functions into unified conductor structures that simultaneously provide electrical connectivity and stress management. The additional conductor areas serve dual purposes: maintaining electrical pathways while creating stress distribution patterns that redirect void diffusion, thereby improving reliability without requiring separate dedicated stress relief structures.
Solution Approach 2:
The patent modifies conductor geometry parameters such as area, shape, and spatial distribution to control stress fields. By adjusting these parameters, the conductor structures redirect void diffusion pathways away from critical vias through stress gradient manipulation, achieving reliability improvement through geometric optimization rather than adding complex functional components.
3Reliability
If conductor geometry is modified to redirect void diffusion, then void-induced failure rates reduce, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality modifications by adding conductor areas or stress relief features at specific locations near vias where void diffusion is most problematic. These localized geometric changes create stress gradients precisely where needed to redirect void diffusion, rather than requiring uniform precision across entire conductor structures, thereby reducing overall manufacturing precision requirements.
Solution Approach 2:
The patent introduces intermediary conductor structures that act as mediators between the via and surrounding interconnect. These intermediate structures absorb and redistribute stress, creating buffer zones that redirect void diffusion pathways. By placing these intermediary elements at strategic locations, the patent achieves void diffusion control without requiring extreme precision in the primary via formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces void-induced failure rates by redirecting void diffusion, enhancing the reliability and longevity of vias in integrated circuits, and minimizing the need for additional vias or interconnect layers, thus reducing manufacturing complexity and cost.
Implementation Method 1
copper atom diffusion along tensile stress gradients
Data Source
AI summary
A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.