Through Substrate Via Void Structure for Thermal Stress Reduction
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Solution Overview
Problem
The integration of chips in 3D structures faces challenges such as stress-induced yield loss due to thermal expansion mismatches between substrate materials and fill materials in through substrate vias, leading to defects like cracks and de-lamination.
Innovation Solution
The formation of through substrate vias with tailored voids and a combination of metal and voids as fill materials, where the voids have negligible thermal expansion, reducing stress concentrations by matching the coefficient of thermal expansion with the silicon substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through substrate vias are filled with metal materials to provide electrical interconnection, then electrical conductivity is improved, but thermal stress concentration increases due to coefficient of thermal expansion mismatch between substrate and fill material
Solution Approach 1:
The patent applies composite materials by combining metal fill material with voids (empty spaces) within the through substrate via structure. This composite configuration allows the metal to provide electrical conductivity while the voids accommodate thermal expansion differences, reducing stress concentration. The metal-void composite structure effectively balances electrical performance with thermal stress management.
Solution Approach 2:
The patent applies local quality by creating non-uniform distribution of fill material within the via. Instead of completely filling the via with metal, voids are strategically positioned at specific locations (such as the bottom or along the sidewalls) where thermal stress accumulation is most problematic. This localized void placement addresses thermal stress concentration at critical points while maintaining overall electrical connectivity through the metal portions.
2Reliability
If through substrate vias are completely filled with metal to ensure electrical connectivity, then electrical conductivity is improved, but manufacturing complexity increases due to stress-induced defects
Solution Approach 1:
The patent applies partial action by filling only a portion of the via with metal material rather than completely filling it. The voids remain as intentional empty spaces. This partial filling approach maintains sufficient electrical connectivity for the application while significantly reducing the thermal mass that causes stress-related manufacturing defects, thereby simplifying the manufacturing process.
3Reliability
If through substrate vias are formed with full metal filling to minimize interconnect resistance, then electrical performance is improved, but yield loss increases due to stress-induced defects
Solution Approach 1:
The patent uses a composite metal-void structure within the via that optimizes the balance between electrical performance and manufacturing yield. The metal portions provide low-resistance electrical paths while the voids reduce thermal stress, preventing cracks and de-lamination that would cause yield loss. This composite approach achieves acceptable interconnect performance with significantly improved manufacturing yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes stress-related defects and enhances the reliability of 3D chip stacking by reducing thermal stress concentrations, thereby improving the yield and performance of semiconductor components.
Implementation Method 1
the voids have negligible thermal expansion, reducing stress concentrations by matching the coefficient of thermal expansion with the silicon substrate
Data Source
AI summary
A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.