Via Wiring Substrate Recess Structure for Crack-Resistant Interconnects
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Solution Overview
Problem
Finer wiring in semiconductor devices increases stress at the interface between via wiring and the wiring layer, leading to potential cracks and reliability issues due to reduced contact area and thermal expansion coefficient mismatches between insulation and solder resist layers.
Innovation Solution
A wiring substrate design featuring a via wiring structure with increased contact area through a recessed and tapered configuration, where the via wiring extends from the solder resist layer to an intermediate position of the via wiring, and the insulation and solder resist layers have different thermal expansion coefficients to manage stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the width of the lower surface of the via wiring is decreased to achieve finer wiring, then the wiring density is improved, but the contact area between the via wiring and the wiring layer is reduced, leading to increased stress concentration and crack formation
Solution Approach 1:
The patent transitions from a single-level via wiring structure to a multi-level structure by introducing a recess in the insulation layer and forming the via wiring at different depths. The via wiring extends into the recess, increasing the contact area with the wiring layer without increasing the planar width, thus resolving the contradiction between wiring fineness and connection reliability
Solution Approach 2:
The patent applies different structural characteristics to different parts of the via wiring system. The upper portion maintains a narrow width for fine wiring, while the lower portion extends into a recess to maximize contact area with the wiring layer. This local differentiation allows the via wiring to simultaneously achieve both fine wiring and reliable connection
2Reliability
If the contact area between via wiring and wiring layer is increased to improve connection reliability, then the stress distribution is improved, but the wiring becomes coarser and manufacturing precision decreases
Solution Approach 1:
Instead of increasing the planar contact area by widening the via wiring, the patent utilizes the vertical dimension by forming a recess in the insulation layer. The via wiring extends into this recess, achieving increased contact area with the wiring layer while maintaining a narrow planar width, thus preserving wiring fineness while improving connection reliability
3Ease of manufacture
If the via wiring is formed directly on the wiring layer without a recess, then the structure is simpler and manufacturing is easier, but stress concentration leads to crack formation under thermal and mechanical loading
Solution Approach 1:
The patent introduces a recess structure in advance, before the via wiring is formed. This recess acts as a stress-distributing feature that prevents stress concentration at the via wiring-wiring layer interface. By preparing this structural cushioning in advance, the design prevents crack formation under subsequent thermal and mechanical loading while maintaining manufacturing feasibility
Data Source
AI summary
A wiring substrate includes a first insulation layer, a first through hole extending through the first insulation layer in a thickness-wise direction, a first via wiring formed in the first through hole, a second insulation layer formed on an upper surface of the first insulation layer, a first recess formed in a lower surface of the second insulation layer and connected to the first through hole, an opening formed in an upper surface of the second insulation layer and connected to the first recess, a second recess formed in an upper surface of the first via wiring and connected to the first recess, a second via wiring formed in the opening, the first recess, and the second recess, and a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring.