Victim Cache Partitioning for ECC-Tolerant Write-Miss Draining
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Solution Overview
Problem
Existing cache systems face challenges in maintaining performance while ensuring fault tolerance due to the timing overhead introduced by error correcting codes (ECC), particularly in high-speed cache memories, which can lead to data corruption from cosmic rays or malicious memory accesses.
Innovation Solution
Implementing a caching system with a first and second sub-cache in parallel, where the second sub-cache stores write-miss data and includes line type bits and an eviction controller to manage write-miss data, allowing for efficient flushing and eviction of such data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting codes (ECC) are implemented in high-speed cache memory to protect against data corruption, then fault tolerance is improved, but timing overhead increases and cache performance deteriorates
Solution Approach 1:
The cache is divided into two separate sub-caches operating in parallel: a first sub-cache for normal cached data and a second sub-cache specifically for write-miss data. This segmentation allows write-miss operations to be handled independently without interfering with normal cache operations, reducing the timing overhead impact on overall cache performance while maintaining fault tolerance through ECC protection in both sub-caches
Solution Approach 2:
The second sub-cache acts as an intermediary structure that temporarily holds write-miss data that misses from the first sub-cache. This intermediary allows the system to handle write-miss operations separately, enabling ECC protection to be applied without blocking normal cache access paths, thus reducing timing overhead while maintaining reliability
2Device complexity
If a single cache structure is used to handle both normal cached data and write-miss data, then device complexity is reduced, but cache performance deteriorates due to interference between different data types
Solution Approach 1:
The cache system is segmented into two independent sub-caches: the first sub-cache handles normal cached data while the second sub-cache handles write-miss data. This segmentation prevents interference between different data types and operations, allowing each sub-cache to be optimized for its specific function, thereby improving overall cache performance despite the increased structural complexity
Solution Approach 2:
The patent introduces a new dimension to the cache structure by adding a second sub-cache that operates in parallel with the first. This dimensional expansion allows the system to handle write-miss operations in a separate space, preventing them from interfering with normal cache operations and improving overall cache productivity
Data Source
AI summary
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.