Parallel Sub-Caches for Victim-Cache Write-Miss Management

Solution Overview

Problem

Existing cache systems face challenges in maintaining performance while ensuring fault tolerance due to the timing overhead introduced by error correcting codes (ECC), particularly in high-speed cache memories, which are susceptible to data corruption from cosmic rays and malicious memory accesses.

Innovation Solution

Implementing a caching system with a first and second sub-cache in parallel, where the second sub-cache stores write-miss data and includes line type bits and an eviction controller to manage write-miss data, allowing efficient handling of write-miss entries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correcting codes (ECC) are implemented in high speed cache memory to detect and correct memory corruption, then fault tolerance is improved, but timing overhead increases and cache performance deteriorates

Engineering Contradiction:

Improvefault toleranceVSAvoidtiming overhead

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The cache is divided into two separate sub-caches operating in parallel: a first sub-cache for normal cached data and a second sub-cache specifically for write-miss data. This segmentation allows write-miss operations to be handled independently without requiring ECC processing on every cache operation, thereby reducing timing overhead while maintaining fault tolerance for critical data

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second sub-cache acts as an intermediary structure that temporarily holds write-miss data before it is committed to main memory. By introducing this intermediate storage layer with dedicated line type bits and eviction controller, the system can manage write-miss entries efficiently without subjecting them to the full ECC processing pipeline, thus reducing timing overhead while maintaining data integrity

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If a single cache structure is used to handle both cached data and write-miss data, then device complexity is reduced, but cache performance deteriorates due to inefficient handling of write-miss entries

Engineering Contradiction:

Improvecache performanceVSAvoidcache structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The cache is divided into two separate sub-caches operating in parallel: a first sub-cache for normal cached data and a second sub-cache specifically for write-miss data. This segmentation allows write-miss operations to be handled independently without requiring ECC processing on every cache operation, thereby reducing timing overhead while maintaining fault tolerance for critical data

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The cache system dynamically manages data between the first and second sub-caches based on operation type. The eviction controller monitors the second sub-cache and dynamically evicts write-miss data when appropriate, allowing the system to adapt to varying workloads and maintain optimal performance without requiring a completely different cache structure

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12455836B2Victim cache that supports draining write-miss entries

Publication Date: 2025.10.28 TEXAS INSTRUMENTS INC

AI summary

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.