Victim Cache Read-Modify-Write Handling for Lower Write Latency

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Solution Overview

Problem

Existing computing systems face significant latency issues due to the time required to access data from main memory, which can be mitigated by incorporating a victim cache to reduce cache miss rates and improve efficiency.

Innovation Solution

Incorporating a victim cache that stores data recently evicted from the main cache, allowing it to service cache misses directly without waiting for the main cache to determine the memory address, thereby reducing latency and increasing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is stored in main memory, then data capacity is sufficient, but access latency is significant

Engineering Contradiction:
Improvedata capacityVSAvoidaccess latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The memory system is segmented into multiple cache levels (L1, L2, victim cache) with different capacities and access speeds. The L1 cache provides fast access for frequently used data, while the victim cache captures evicted data that may be reused soon, creating a hierarchical structure that balances capacity and latency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The victim cache is nested within the L1 cache structure, acting as an extension that captures evicted data. When L1 evicts data, it first checks the victim cache before proceeding to L2, creating a nested lookup hierarchy that reduces latency for recently evicted data without requiring access to slower L2 or main memory.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Loss of time

If a standard cache is used, then cache latency is reduced, but conflict misses increase

Engineering Contradiction:
Improvecache latencyVSAvoidconflict miss rate
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The victim cache acts as an intermediary between the L1 cache and L2 cache. It captures data evicted from L1 and serves as a buffer that can satisfy subsequent accesses to this data, reducing conflict misses by providing an additional lookup opportunity before accessing L2.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of permanently discarding data when it is evicted from L1, the victim cache recovers and temporarily stores this data. This allows the system to recover from conflict misses by retrieving data from the victim cache if it was evicted recently and is still needed.

Inventive Principle:
Principle #34Discarding and recovering

3Productivity

If victim cache is added to reduce conflict misses, then cache efficiency improves, but device complexity increases

Engineering Contradiction:
Improvecache efficiencyVSAvoidcache architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The victim cache is merged with the L1 cache structure, sharing control logic and tag comparison resources. The victim cache uses the same tag array and control unit as L1, eliminating the need for separate control logic and reducing overall complexity despite adding storage capacity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The L1 cache control logic serves multiple functions: it manages both the primary L1 cache and the victim cache, handling tag comparisons, data retrieval, and eviction decisions for both structures. This multi-functionality reduces the need for duplicate control units and simplifies the overall architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12625822B2Methods and apparatus to facilitate read-modify-write support in a victim cache
Publication Date: 2026.05.12 TEXAS INSTRUMENTS INC
  • US12625822B2 patent drawing
  • US12625822B2 patent drawing
  • US12625822B2 patent drawing

AI summary

Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.