DRAM Victim Row Protection via Cache Copying for Rowhammer Mitigation

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Solution Overview

Problem

Existing technologies are ineffective in detecting and mitigating rowhammer attacks, which exploit charge leakage in DRAM to corrupt or read sensitive data by repeatedly accessing adjacent memory rows.

Innovation Solution

An apparatus and method that includes victim row identification circuitry to detect rapid access requests to a DRAM row and victim row protection circuitry to copy data from potentially vulnerable rows to a cache storage, preventing the attack from succeeding by accessing the data from the cache instead of the DRAM.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is stored only in DRAM, then memory access speed is fast, but data can be corrupted by rowhammer attacks through charge leakage

Engineering Contradiction:
Improvedata integrityVSAvoidmemory system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent creates a duplicate copy of the victim row data and stores it in a separate safe location (different bank or row). This copy serves as a backup that is protected from rowhammer attacks on the original row, allowing data integrity verification and recovery without increasing DRAM capacity requirements

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces an intermediary protection mechanism that monitors access patterns to detected hammer rows and automatically redirects or blocks accesses to victim rows. This intermediary layer prevents direct attack propagation while maintaining normal memory operation for legitimate workloads

Inventive Principle:
Principle #24Intermediary (Mediator)

2Difficulty of detecting and measuring

If access rate monitoring is implemented to detect rowhammer attacks, then attack detection capability is improved, but processing overhead and system complexity increase

Engineering Contradiction:
Improveattack detection capabilityVSAvoiddetection system complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The memory system performs self-monitoring of access patterns to its own rows, with each memory controller capable of detecting rapid access sequences to its managed rows. This self-service detection approach eliminates the need for external monitoring hardware and enables distributed attack detection across the memory subsystem

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements preliminary protection by pre-identifying victim rows adjacent to detected hammer rows and proactively copying their data to safe locations before the attack can corrupt the data. This preliminary action prevents data corruption rather than merely detecting it after the fact

Inventive Principle:
Principle #10Preliminary action

3Reliability

If victim row data is copied to cache storage for protection, then data security is improved, but memory access time may increase due to cache miss penalties

Engineering Contradiction:
Improvedata protectionVSAvoidmemory access time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial protection by selectively copying only victim row data (rows adjacent to detected hammer rows) to safe locations, rather than copying all DRAM data. This targeted approach provides sufficient protection against rowhammer attacks while minimizing the performance impact of additional memory operations

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11461464B2Methods and apparatus for memory attack detection
Publication Date: 2022.10.04 ARM LTD
  • US11461464B2 patent drawing
  • US11461464B2 patent drawing
  • US11461464B2 patent drawing

AI summary

Aspects of the present disclosure relate to an apparatus comprising processing circuitry, a cache storage, victim row identification circuitry and victim row protection circuitry. The victim row identification circuitry is configured to detect a rapid rate of access requests from the processing circuitry to a given row of a DRAM and, responsive to said detecting, identify at least one victim row associated with said given row. The victim row protection circuitry is configured to copy data stored within said at least one victim row to the cache storage.